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path: root/src/intel/compiler/brw_fs_nir.cpp
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* spirv/i965/anv: Relax push constant offset assertions being 32-bit alignedJose Maria Casanova Crespo2018-02-281-5/+10
* i965/fs: Support 16-bit store_ssbo with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-7/+15
* i965/fs: Support 16-bit do_read_vector with VK_KHR_relaxed_block_layoutJose Maria Casanova Crespo2018-02-281-14/+37
* i965/fs: shuffle_32bit_load_result_to_16bit_data now skips componentsJose Maria Casanova Crespo2018-02-281-2/+4
* isl/i965/fs: SSBO/UBO buffers need size padding if not multiple of 32-bitJose Maria Casanova Crespo2018-02-281-1/+30
* i965/compiler: clean up nir_intrinsic_load_input for vertex shadersIago Toral Quiroga2018-02-141-11/+2
* intel/compiler: fix first_component for 64-bit types on vertex inputsIago Toral Quiroga2018-02-141-0/+3
* i965/fs: Use UW types when using V immediatesJason Ekstrand2018-01-111-2/+2
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* i965/fs: Use untyped_surface_read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-7/+20
* i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit regJose Maria Casanova Crespo2017-12-061-15/+43
* i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit componentsJose Maria Casanova Crespo2017-12-061-0/+60
* i965/fs: Use byte scattered read for 16-bit load_ssboJose Maria Casanova Crespo2017-12-061-1/+13
* i965/fs: Predicate byte scattered writes if neededAlejandro Piñeiro2017-12-061-1/+14
* i965/fs: Use byte_scattered_write on 16-bit store_ssboAlejandro Piñeiro2017-12-061-20/+45
* i965/fs: Enable rounding mode on f2f16 opsAlejandro Piñeiro2017-12-061-0/+18
* i965/fs: Handle 32-bit to 16-bit conversionsAlejandro Piñeiro2017-12-061-0/+25
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-151-47/+0
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-141-2/+23
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-141-4/+4
* intel/fs/nir: Return Q types from brw_reg_type_for_bit_sizeJason Ekstrand2017-11-071-2/+2
* intel/fs/nir: Use Q immediates for load_const on gen8+Jason Ekstrand2017-11-071-3/+11
* intel/fs/nir: Setup immediates based on type in i2b and f2bJason Ekstrand2017-11-071-1/+2
* nir,intel/compiler: Use a fixed subgroup sizeJason Ekstrand2017-11-071-4/+0
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-4/+4
* intel/compiler/fs: Set up subgroup invocation as a system valueJason Ekstrand2017-11-071-13/+21
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-071-4/+4
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-071-0/+14
* intel/fs: use pull constant locations to check for first compile of a shaderJason Ekstrand2017-11-071-1/+4
* intel/fs: Retype dest to match value in read[First]InvocationJason Ekstrand2017-11-071-4/+2
* intel/fs: Uniformize the index in readInvocationJason Ekstrand2017-11-071-1/+1
* i965/fs/nir: Don't stomp 64-bit values to D in get_nir_srcJason Ekstrand2017-11-071-13/+24
* i965/fs/nir: Minor refactor of store_outputJason Ekstrand2017-11-071-4/+3
* i965/fs: Return a fs_reg from shuffle_64bit_data_for_32bit_writeJason Ekstrand2017-11-071-25/+9
* i965/fs/nir: Simplify 64-bit store_outputJason Ekstrand2017-11-071-19/+6
* intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/allJason Ekstrand2017-11-071-9/+33
* intel/fs: Use an explicit D type for vote any/all/eq intrinsicsJason Ekstrand2017-11-071-0/+6
* intel/fs: Don't stomp f0.1 in SIMD16 ballotJason Ekstrand2017-11-071-2/+9
* intel/fs: Use ANY/ALL32 predicates in SIMD32Jason Ekstrand2017-11-071-12/+30
* i965/fs: Add brw_reg_type_from_bit_size utility methodAlejandro Piñeiro2017-10-251-5/+64
* i965/fs/nir: Use the nir_src_bit_size helperJason Ekstrand2017-10-251-9/+3
* i965/fs: remove setting default LOD in the backendSamuel Iglesias Gonsálvez2017-10-201-9/+0
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
* i965/tes: account for the fact that dvec3/4 inputs take two slotsIago Toral Quiroga2017-10-101-2/+7
* i965/fs: Rewrite fsign64 to skip the float -> double conversionMatt Turner2017-10-041-41/+9
* i965/fs: Unpack count argument to 64-bit shift ops on AtomMatt Turner2017-10-041-6/+28
* i965/fs: force pull model for 64-bit GS inputsIago Toral Quiroga2017-09-291-1/+3
* i965/fs: Match destination type to size for ballotMatt Turner2017-07-201-1/+5
* i965/fs: Implement ARB_shader_ballot operationsMatt Turner2017-07-201-0/+46
* nir: Add system values from ARB_shader_ballotMatt Turner2017-07-201-1/+1
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