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path: root/src/intel/compiler/brw_fs_generator.cpp
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* intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcodeMatt Turner2018-02-281-6/+6
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-281-3/+45
* intel/compiler/fs: Return multiple_instructions_emitted from generate_linterpMatt Turner2018-02-281-3/+7
* intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pairMatt Turner2018-02-281-2/+11
* i965: Drop render_target_start from binding table struct.Kenneth Graunke2018-01-221-4/+2
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"Anuj Phogat2017-12-221-8/+4
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+5
* intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.Rafael Antognolli2017-12-011-0/+13
* intel: fix disasm_info memory leaksTapani Pälli2017-11-211-1/+1
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-171-11/+10
* i965: Move common code out of #ifdefMatt Turner2017-11-171-5/+2
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-141-13/+3
* intel/fs: Don't use automatic exec size inferenceJason Ekstrand2017-11-071-3/+9
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+7
* intel/fs: Fix MOV_INDIRECT for 64-bit values on little-coreJason Ekstrand2017-11-071-36/+39
* intel/compiler: Add some restrictions to MOV_INDIRECT and BROADCASTJason Ekstrand2017-11-071-0/+2
* intel/fs: Use a pure vertical stride for large register stridesJason Ekstrand2017-11-071-3/+13
* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-251-1/+0
* i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner2017-10-201-4/+8
* i965/fs: Don't apply POW/FDIV workaround on Gen10+Matt Turner2017-10-041-0/+1
* i965: Normalize types for FBL, FBH, etcMatt Turner2017-09-301-8/+6
* i965: Stop using wm_prog_data->binding_table.render_target_start.Kenneth Graunke2017-08-231-2/+7
* i965: Pass pointer and end of assembly to brw_validate_instructionsMatt Turner2017-05-151-2/+8
* i965/fs: Get 64-bit indirect moves working on IVB.Francisco Jerez2017-04-141-2/+25
* i965/fs: fix dst stride in IVB/BYT type conversionsJuan A. Suarez Romero2017-04-141-27/+41
* i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.Matt Turner2017-04-141-0/+13
* i965/fs: double regioning parameters and execsize for DF in IVB/BYTJuan A. Suarez Romero2017-04-141-7/+43
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+2126
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