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path: root/src/intel/compiler/brw_fs_generator.cpp
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* intel/fs: Initialize mlen for gen7 varying pull constant load messages.Francisco Jerez2018-07-091-6/+4
* intel/eu: Use descriptor constructors for dataport read messages.Francisco Jerez2018-07-091-16/+16
* intel/eu: Use descriptor constructors for sampler messages.Francisco Jerez2018-07-091-40/+32
* intel/eu: Provide desc immediate argument up front to brw_send_indirect_messa...Francisco Jerez2018-07-091-3/+3
* intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand2018-06-281-28/+0
* intel/fs: Disable opt_sampler_eot() in 32-wide dispatch.Francisco Jerez2018-06-281-0/+5
* intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinatesJason Ekstrand2018-06-281-9/+54
* intel/fs: Rework INTERPOLATE_AT_PER_SLOT_OFFSETFrancisco Jerez2018-06-281-3/+5
* intel/fs: Add the group to the flag subreg number on SNB and olderJason Ekstrand2018-06-281-1/+7
* intel/fs: Fix FB write message control codegen for SIMD32.Francisco Jerez2018-06-281-18/+34
* intel/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.Francisco Jerez2018-06-281-11/+13
* intel/fs: Remove program key argument from generator.Francisco Jerez2018-06-281-2/+1
* intel/fs: Set up FB write message headers in the visitorJason Ekstrand2018-06-281-66/+0
* intel/fs: Pull FB write implied headers from src[0]Jason Ekstrand2018-06-281-9/+6
* intel/eu: Add some brw_get_default_ helpersJason Ekstrand2018-06-041-2/+2
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-1/+6
* intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.Francisco Jerez2018-05-291-5/+1
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-291-3/+0
* intel/fs: Use groups for SIMD16 LINTERP on gen11+Jason Ekstrand2018-05-291-4/+5
* intel/fs: Assert that the gen4-6 plane restrictions are followedJason Ekstrand2018-05-291-2/+8
* intel/compiler: Silence unused parameter warnings in generate_foo methodsIan Romanick2018-04-241-4/+4
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-081-0/+6
* intel/fs: Add support for subgroup quad operationsJason Ekstrand2018-03-071-0/+20
* intel/fs: Add a couple of simple helper opcodesJason Ekstrand2018-03-071-0/+47
* i965/fs: Add support for nir_intrinsic_shuffleJason Ekstrand2018-03-071-0/+104
* intel: Drop program size pointer from vec4/fs assembly getters.Kenneth Graunke2018-03-021-2/+2
* intel/eu: Plumb header present bit to codegen helpers for HDC messages.Francisco Jerez2018-03-021-6/+14
* intel/ir: Allow representing additional flag subregisters in the IR.Francisco Jerez2018-03-021-2/+2
* intel/fs: Set up sampler message headers in the visitor on gen7+Jason Ekstrand2018-03-011-18/+3
* intel/compiler: Lower flrp32 on Gen11+Matt Turner2018-02-281-1/+1
* intel/compiler/fs: Implement ddy without using align16 for Gen11+Matt Turner2018-02-281-8/+38
* intel/compiler/fs: Simplify ddx/ddy code generationMatt Turner2018-02-281-42/+21
* intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcodeMatt Turner2018-02-281-6/+6
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-281-3/+45
* intel/compiler/fs: Return multiple_instructions_emitted from generate_linterpMatt Turner2018-02-281-3/+7
* intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pairMatt Turner2018-02-281-2/+11
* i965: Drop render_target_start from binding table struct.Kenneth Graunke2018-01-221-4/+2
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"Anuj Phogat2017-12-221-8/+4
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+5
* intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.Rafael Antognolli2017-12-011-0/+13
* intel: fix disasm_info memory leaksTapani Pälli2017-11-211-1/+1
* i965: Rewrite disassembly annotation codeMatt Turner2017-11-171-11/+10
* i965: Move common code out of #ifdefMatt Turner2017-11-171-5/+2
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-141-13/+3
* intel/fs: Don't use automatic exec size inferenceJason Ekstrand2017-11-071-3/+9
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+7
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