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path: root/src/intel/compiler/brw_eu_emit.c
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* intel/eu: Fix pixel interpolator queries for SIMD32.Francisco Jerez2018-06-281-1/+2
* intel/eu: Return new instruction to caller from brw_fb_WRITE().Francisco Jerez2018-06-281-11/+13
* intel/eu: Switch to a logical state stackJason Ekstrand2018-06-041-71/+3
* intel/eu: Set flag [sub]register number differently for 3srcJason Ekstrand2018-06-041-3/+10
* intel/eu: Copy fields manually in brw_next_insnJason Ekstrand2018-06-041-1/+94
* intel/eu: Add some brw_get_default_ helpersJason Ekstrand2018-06-041-53/+45
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-3/+4
* intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0Jason Ekstrand2018-05-221-0/+2
* intel/compiler/icl: Clear "null render target" bit in extended message descri...Jason Ekstrand2018-03-221-0/+3
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-081-0/+1
* intel/compiler: Memory fence commit must always be enabled for gen10+Anuj Phogat2018-03-021-1/+3
* intel/eu: Plumb header present bit to codegen helpers for HDC messages.Francisco Jerez2018-03-021-12/+18
* intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_...Francisco Jerez2018-03-021-2/+3
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-281-1/+1
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-281-2/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+32
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+44
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+33
* intel/eu: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+9
* intel/eu: Make automatic exec sizes a configurable optionJason Ekstrand2017-11-071-14/+18
* intel/eu: Fix broadcast instruction for 64-bit values on little-coreJason Ekstrand2017-11-071-2/+24
* intel/eu: Just modify the offset in brw_broadcastJason Ekstrand2017-11-071-4/+5
* intel/compiler: Add some restrictions to MOV_INDIRECT and BROADCASTJason Ekstrand2017-11-071-0/+16
* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-251-1/+1
* i965: Add align1 ternary instruction emission supportMatt Turner2017-10-201-55/+160
* i965: Add functions to abstract access to 3src register typesMatt Turner2017-10-201-20/+2
* i965: Rename brw_inst's functions that access the 3src register typeMatt Turner2017-10-201-8/+8
* i965: Rename brw_inst 3src functions in preparation for align1Matt Turner2017-10-201-24/+24
* i965: Remove validate_reg()Matt Turner2017-10-041-80/+0
* i965: Switch to using the logical register typesMatt Turner2017-08-211-10/+3
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-211-9/+9
* i965: Extract functions dealing with register types to separate fileMatt Turner2017-08-211-102/+0
* i965: Reverse file/type arguments to register type functionsMatt Turner2017-08-211-6/+8
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-211-55/+54
* i965: Reorder brw_reg_type enum valuesMatt Turner2017-08-211-6/+0
* i965: Validate destination restrictions with vector immediatesMatt Turner2017-08-211-12/+1
* i965: Move compaction "prepass" into brw_eu_compact.cMatt Turner2017-08-211-70/+2
* intel/compiler: remove check unsigned is >= 0Lionel Landwerlin2017-07-131-1/+1
* i965: Use correct VertStride on align16 instructions.Matt Turner2017-04-141-10/+34
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-141-1/+27
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+3675
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