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path: root/src/intel/compiler/brw_eu_emit.c
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* intel/eu: force stride of 2 on NULL register for Byte instructionsIago Toral Quiroga2019-04-181-0/+11
* intel/compiler: set correct precision fields for 3-source float instructionsIago Toral Quiroga2019-04-181-0/+16
* intel/compiler: allow half-float on 3-source instructions since gen8Iago Toral Quiroga2019-04-181-1/+2
* intel/compiler: handle extended math restrictions for half-floatIago Toral Quiroga2019-04-181-2/+4
* intel/vec4: Drop dead code for handling typed surface messagesJason Ekstrand2019-02-281-89/+0
* intel/eu: Add an EOT parameter to send_indirect_[split]_messageJason Ekstrand2019-02-251-10/+15
* intel/eu: Add support for the SENDS[C] messagesJason Ekstrand2019-01-291-5/+136
* intel/inst: Indent some codeJason Ekstrand2019-01-291-177/+183
* intel/fs: Use SHADER_OPCODE_SEND for surface messagesJason Ekstrand2019-01-291-72/+0
* intel/eu: Rework surface descriptor helpersJason Ekstrand2019-01-291-234/+21
* intel/eu: Add has_simd4x2 bools to surface_write functionsJason Ekstrand2019-01-291-6/+8
* intel/fs: Take an explicit exec size in brw_surface_payload_size()Jason Ekstrand2019-01-291-20/+39
* intel/compiler: Reset default flag register in brw_find_live_channel()Matt Turner2019-01-231-2/+11
* intel/eu: Stop overriding exec sizes in send_indirect_messageJason Ekstrand2019-01-181-3/+0
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
* intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.Francisco Jerez2019-01-091-7/+4
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
* intel/compiler: Change src1 reg type to unsigned doublewordSagar Ghuge2018-10-231-1/+1
* intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...Ian Romanick2018-08-221-0/+47
* intel/eu: Assert that the instruction is send-like in brw_set_desc_ex().Francisco Jerez2018-07-091-2/+3
* intel/eu: Get rid of the return value of brw_send_indirect_message().Francisco Jerez2018-07-091-14/+3
* intel/eu: Get rid of the return value of brw_send_indirect_surface_message().Francisco Jerez2018-07-091-10/+6
* intel/eu: Use descriptor constructors for dataport typed surface messages.Francisco Jerez2018-07-091-47/+35
* intel/eu: Use descriptor constructors for dataport scattered byte surface mes...Francisco Jerez2018-07-091-33/+27
* intel/eu: Use descriptor constructors for dataport untyped surface messages.Francisco Jerez2018-07-091-50/+38
* intel/eu: Provide single descriptor argument to brw_send_indirect_surface_mes...Francisco Jerez2018-07-091-29/+36
* intel/eu: Use descriptor constructors for pixel interpolator messages.Francisco Jerez2018-07-091-14/+12
* intel/eu: Use descriptor constructors for dataport write messages.Francisco Jerez2018-07-091-74/+26
* intel/eu: Use descriptor constructors for dataport read messages.Francisco Jerez2018-07-091-52/+25
* intel/eu: Use descriptor constructors for sampler messages.Francisco Jerez2018-07-091-39/+6
* intel/eu: Provide desc immediate argument up front to brw_send_indirect_messa...Francisco Jerez2018-07-091-5/+6
* TRIVIAL: intel/eu: Use a local devinfo variable in brw_shader_time_add().Francisco Jerez2018-07-091-5/+6
* intel/eu: Use brw_set_desc() along with a helper to set common descriptor con...Francisco Jerez2018-07-091-69/+39
* intel/eu: Define helper to specify the descriptor immediates of a SEND instru...Francisco Jerez2018-07-091-0/+17
* intel/eu: Fix pixel interpolator queries for SIMD32.Francisco Jerez2018-06-281-1/+2
* intel/eu: Return new instruction to caller from brw_fb_WRITE().Francisco Jerez2018-06-281-11/+13
* intel/eu: Switch to a logical state stackJason Ekstrand2018-06-041-71/+3
* intel/eu: Set flag [sub]register number differently for 3srcJason Ekstrand2018-06-041-3/+10
* intel/eu: Copy fields manually in brw_next_insnJason Ekstrand2018-06-041-1/+94
* intel/eu: Add some brw_get_default_ helpersJason Ekstrand2018-06-041-53/+45
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-3/+4
* intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0Jason Ekstrand2018-05-221-0/+2
* intel/compiler/icl: Clear "null render target" bit in extended message descri...Jason Ekstrand2018-03-221-0/+3
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-081-0/+1
* intel/compiler: Memory fence commit must always be enabled for gen10+Anuj Phogat2018-03-021-1/+3
* intel/eu: Plumb header present bit to codegen helpers for HDC messages.Francisco Jerez2018-03-021-12/+18
* intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_...Francisco Jerez2018-03-021-2/+3
* intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+Matt Turner2018-02-281-1/+1
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-281-2/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
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