| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | i965: Add align1 ternary instruction disassembler support | Matt Turner | 2017-10-20 | 1 | -11/+0 |
| * | i965: Add align1 ternary instruction field encodings | Matt Turner | 2017-10-20 | 1 | -0/+35 |
| * | i965: Hide the register type hardware encodings | Matt Turner | 2017-08-21 | 1 | -31/+0 |
| * | i965: Use separate enums for register vs immediate types | Matt Turner | 2017-08-21 | 1 | -18/+30 |
| * | i965: Move SF compilation to the compiler | Jason Ekstrand | 2017-05-26 | 1 | -0/+2 |
| * | i965: Move enums to brw_compiler.h. | Rafael Antognolli | 2017-05-03 | 1 | -21/+0 |
| * | i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type | Samuel Iglesias Gonsálvez | 2017-04-14 | 1 | -1/+3 |
| * | intel: fix compiler build | Iago Toral Quiroga | 2017-03-13 | 1 | -0/+7 |
| * | i965: Move the back-end compiler to src/intel/compiler | Jason Ekstrand | 2017-03-13 | 1 | -0/+1246 |
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