index
:
mesa.git
gallium_va_encpackedheader01
master
Unnamed repository; edit this file 'description' to name the repository.
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
intel
/
compiler
/
brw_eu_defines.h
Commit message (
Expand
)
Author
Age
Files
Lines
*
intel: Use TXS for image_size when we have a typed surface
Jason Ekstrand
2018-08-29
1
-0
/
+2
*
intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...
Ian Romanick
2018-08-22
1
-1
/
+11
*
intel/ir: Uncomment definition of several unused hardware opcodes.
Francisco Jerez
2018-07-09
1
-14
/
+14
*
intel/eu: Define SET_BITS helper more easily reusable than SET_FIELD.
Francisco Jerez
2018-07-09
1
-0
/
+7
*
intel/fs: Get rid of MOV_DISPATCH_TO_FLAGS
Jason Ekstrand
2018-06-28
1
-1
/
+0
*
i965: Add ARB_fragment_shader_interlock support.
Plamena Manolova
2018-06-01
1
-0
/
+2
*
intel/fs: Replace the CINTERP opcode with a simple MOV
Francisco Jerez
2018-05-29
1
-1
/
+0
*
intel/fs: Add support for subgroup quad operations
Jason Ekstrand
2018-03-07
1
-0
/
+5
*
intel/fs: Add a couple of simple helper opcodes
Jason Ekstrand
2018-03-07
1
-0
/
+13
*
i965/fs: Add support for nir_intrinsic_shuffle
Jason Ekstrand
2018-03-07
1
-0
/
+9
*
i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.
Kenneth Graunke
2017-12-30
1
-3
/
+2
*
i965/fs: Add byte scattered read message and fs support
Jose Maria Casanova Crespo
2017-12-06
1
-0
/
+2
*
i965/fs: Add byte scattered write message and fs support
Jose Maria Casanova Crespo
2017-12-06
1
-0
/
+20
*
i965/fs: Add remove_extra_rounding_modes optimization
Alejandro Piñeiro
2017-12-06
1
-0
/
+1
*
i965/fs: Define new shader opcode to set rounding modes
Alejandro Piñeiro
2017-12-06
1
-0
/
+16
*
i965: Add align1 ternary instruction disassembler support
Matt Turner
2017-10-20
1
-11
/
+0
*
i965: Add align1 ternary instruction field encodings
Matt Turner
2017-10-20
1
-0
/
+35
*
i965: Hide the register type hardware encodings
Matt Turner
2017-08-21
1
-31
/
+0
*
i965: Use separate enums for register vs immediate types
Matt Turner
2017-08-21
1
-18
/
+30
*
i965: Move SF compilation to the compiler
Jason Ekstrand
2017-05-26
1
-0
/
+2
*
i965: Move enums to brw_compiler.h.
Rafael Antognolli
2017-05-03
1
-21
/
+0
*
i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's type
Samuel Iglesias Gonsálvez
2017-04-14
1
-1
/
+3
*
intel: fix compiler build
Iago Toral Quiroga
2017-03-13
1
-0
/
+7
*
i965: Move the back-end compiler to src/intel/compiler
Jason Ekstrand
2017-03-13
1
-0
/
+1246