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path: root/src/intel/compiler/brw_eu_defines.h
Commit message (Expand)AuthorAgeFilesLines
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-3/+2
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+2
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+20
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-061-0/+1
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+16
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-201-11/+0
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Hide the register type hardware encodingsMatt Turner2017-08-211-31/+0
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-211-18/+30
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-261-0/+2
* i965: Move enums to brw_compiler.h.Rafael Antognolli2017-05-031-21/+0
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-1/+3
* intel: fix compiler buildIago Toral Quiroga2017-03-131-0/+7
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+1246
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