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src
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intel
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compiler
/
brw_disasm.c
Commit message (
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Author
Age
Files
Lines
*
intel/compiler: fix 64bit value prints on 32bit
Grazvydas Ignotas
2018-02-10
1
-2
/
+2
*
i965: Add align1 ternary instruction disassembler support
Matt Turner
2017-10-20
1
-64
/
+288
*
i965: Add align1 ternary instruction support to conversion functions
Matt Turner
2017-10-20
1
-12
/
+4
*
i965: Rename brw_inst's functions that access the 3src register type
Matt Turner
2017-10-20
1
-8
/
+8
*
i965: Rename brw_inst 3src functions in preparation for align1
Matt Turner
2017-10-20
1
-23
/
+23
*
i965: Print subreg in units of type-size on ternary instructions
Matt Turner
2017-10-20
1
-5
/
+26
*
i965: Fix support for disassembling 64-bit integer immediates
Matt Turner
2017-10-04
1
-2
/
+2
*
i965: Stop using hardware register types directly
Matt Turner
2017-08-21
1
-28
/
+19
*
i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c
Matt Turner
2017-08-21
1
-39
/
+33
*
i965: Rename brw_inst's functions that access the register type
Matt Turner
2017-08-21
1
-11
/
+11
*
i965: Reverse file/type arguments to register type functions
Matt Turner
2017-08-21
1
-2
/
+2
*
i965: Add support for disassembling 64-bit integer immediates
Matt Turner
2017-08-21
1
-0
/
+6
*
i965: Use separate enums for register vs immediate types
Matt Turner
2017-08-21
1
-22
/
+24
*
i965: Fix indentation
Matt Turner
2017-08-02
1
-6
/
+6
*
intel/compiler: Make brw_disasm take const assembly
Jason Ekstrand
2017-05-26
1
-10
/
+10
*
i965/disasm: also print nibctrl in IVB for execsize=8
Iago Toral Quiroga
2017-04-14
1
-3
/
+3
*
i965: Move the back-end compiler to src/intel/compiler
Jason Ekstrand
2017-03-13
1
-0
/
+1646