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path: root/src/intel/compiler/brw_compiler.c
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* intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardwareIan Romanick2019-08-281-0/+1
* st,i965: Stop looping on 64-bit loweringJason Ekstrand2019-07-161-1/+3
* nir,intel: Add support for lowering 64-bit nir_opt_extract_*Jason Ekstrand2019-07-151-1/+2
* nir: intel/vec4: Add flag to disable some algebraic optimizationsIan Romanick2019-07-111-0/+1
* intel/compiler: Add a "base class" for program keysJason Ekstrand2019-07-101-17/+0
* intel/compiler: Emit ROR and ROL instructionSagar Ghuge2019-07-011-0/+2
* nir: Combine lower_fmod16/32 back into a single lower_fmod.Kenneth Graunke2019-06-051-2/+1
* nir: Drop lower_fmod64 option.Kenneth Graunke2019-06-051-1/+0
* iris: Ask st to vectorize our IO.Kenneth Graunke2019-05-281-0/+1
* intel: Move brw_prog_key_set_id from i965 to the compiler.Kenneth Graunke2019-05-211-0/+17
* intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8Kenneth Graunke2019-05-141-0/+3
* intel/compiler: Use the flrp lowering pass for all stages on Gen4 and Gen5Ian Romanick2019-05-061-10/+4
* nir: nir_shader_compiler_options: drop native_integersChristian Gmeiner2019-05-071-1/+0
* intel/compiler: Lower ffma on Gen4 and Gen5Ian Romanick2019-04-231-0/+4
* intel/compiler: Don't have sepearate, per-Gen nir_optionsIan Romanick2019-04-231-31/+11
* intel/common: move gen_debug to intel/devMark Janes2019-04-101-1/+1
* intel/fs: Add support for CS to group invocations in quadsCaio Marcelo de Oliveira Filho2019-04-081-1/+0
* compiler/nir: add lowering for 16-bit flrpIago Toral Quiroga2019-03-251-0/+1
* compiler/nir: add lowering option for 16-bit fmodIago Toral Quiroga2019-03-251-0/+1
* i965: Stop setting LowerBuferInterfaceBlocksJason Ekstrand2019-03-151-1/+0
* intel/debug: Add a debug flag to force software fp64Jason Ekstrand2019-03-061-1/+1
* nir/glsl: Add another way of doing lower_imul64 for gen8+Sagar Ghuge2019-03-041-0/+7
* intel/compiler: Move int64/doubles lowering optionsJordan Justen2019-03-021-4/+37
* intel: Use the NIR lowering for isign.Eric Anholt2019-02-141-0/+1
* intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_valuesJason Ekstrand2018-11-191-0/+1
* nir: Drop the vs_inputs_dual_locations optionJason Ekstrand2018-09-061-3/+0
* intel/compiler: Add brw_get_compiler_config_value for disk cacheJordan Justen2018-08-011-0/+27
* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-021-1/+2
* anv: Trivially implement VK_KHR_device_groupJason Ekstrand2018-03-071-0/+1
* intel/compiler: Re-add .vs_inputs_dual_locations = trueMatt Turner2018-02-281-0/+1
* intel/compiler: Lower flrp32 on Gen11+Matt Turner2018-02-281-13/+22
* nir: add lower_ldexp to nir compiler optionsTimothy Arceri2018-02-281-0/+1
* nir: add vs_inputs_dual_locations compiler optionTimothy Arceri2018-01-301-0/+3
* nir/lower_subgroups: Lower ballot intrinsics to the specified bit sizeJason Ekstrand2017-11-071-1/+0
* nir: Add a new subgroups lowering passJason Ekstrand2017-11-071-3/+0
* intel/compiler: Add functions to get prog_data and prog_key sizes for a stageJordan Justen2017-10-311-0/+36
* i965: Set lower_vote_trivial in vector_nir_options_gen6 too.Kenneth Graunke2017-07-211-0/+1
* i965/fs: Match destination type to size for ballotMatt Turner2017-07-201-1/+1
* nir: Reduce destination size of ballot intrinsic when possibleMatt Turner2017-07-201-0/+1
* i965/fs: Implement ARB_shader_ballot operationsMatt Turner2017-07-201-0/+1
* i965/vec4: Lower ARB_shader_group_vote intrinsicsMatt Turner2017-07-201-0/+1
* i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.Kenneth Graunke2017-06-051-1/+1
* i965: Ignore INTEL_SCALAR_* debug variables on Gen10+.Kenneth Graunke2017-05-291-10/+16
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+160
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