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* intel/tools: Decode PS kernels on SNBJason Ekstrand2019-09-061-1/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNBJason Ekstrand2019-09-061-0/+15
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen12: Add L3 configurationsAnuj Phogat2019-09-061-1/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/l3: Don't assert on gen12 (use gen11 config temporarily)Jordan Justen2019-08-281-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Decode SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-0/+8
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* meson,i965: Link with android deps when building for android.Bas Nieuwenhuizen2019-08-071-0/+10
| | | | | | | | | | | The DBG marco in brw_blorp.c ends up calling an android log function: error: undefined reference to '__android_log_print' v2: On suggestion from Lionel, hang the Android dependency onto a new libintel_common dependency. Reviewed-by: Lionel Landwerlin <[email protected]>
* meson: drop unused dep_{thread,dl}Eric Engestrom2019-08-031-1/+1
| | | | | | | | Unused as of last commit. Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Eric Anholt <[email protected]> Tested-by: Vinson Lee <[email protected]>
* meson: replace libmesa_util with idep_mesautilEric Engestrom2019-08-031-3/+4
| | | | | | | | | | | This automates the include_directories and dependencies tracking so that all users of libmesa_util don't need to add them manually. Next commit will remove the ones that were only added for that reason. Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Eric Anholt <[email protected]> Tested-by: Vinson Lee <[email protected]>
* intel/device: rename gen_get_device_infoMark Janes2019-08-011-1/+1
| | | | | | | | | | | | | | | | | | Rename the original device info initialization routine so callers don't mistakenly call the wrong one: gen_get_device_info_from_fd: Queries kernel for full device info, including topology details. gen_get_device_info_from_pci_id: Partially initializes device info based on PCI ID lookup, when the kernel is not available. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: provide common ioctl routineMark Janes2019-08-011-0/+16
| | | | | | | | | | | i965 links against libdrm for drmIoctl, but anv and iris both re-implement this routine to avoid the dependency. intel/dev also needs an ioctl wrapper, so lets share the same implementation everywhere. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/mi: only resolve to a temp register if source isn't in memoryEric Engestrom2019-07-291-1/+1
| | | | | | | | | aka. fix a s/||/&&/ typo Fixes: 74063ee61aadd1371a9b ("intel/mi: Add a new gen_mi_store_if() helper.") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/mi: Add a unit test for gen_mi_store_if().Kenneth Graunke2019-07-251-0/+43
| | | | | | This tests that predicated stores work. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add a new gen_mi_store_if() helper.Kenneth Graunke2019-07-251-0/+53
| | | | | | | This performs predicated MI_STORE_REGISTER_MEM commands, assuming that the condition is already loaded into MI_PREDICATE_DATA. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add gen_mi_nz() and gen_mi_z() helpers.Kenneth Graunke2019-07-251-0/+20
| | | | | | These provide comparisons against zero. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Add a gen_mi_ior() to go with gen_mi_iand()Kenneth Graunke2019-07-251-0/+8
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/mi: Optimize away LOAD_REGISTER_REG from a register to itselfKenneth Graunke2019-07-251-3/+5
| | | | | | | | We might want to resolve something to be in a particular register, so we can access it outside of the gen_mi framework...but it may already be in that register, at which point there's no work to do. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel/genxml: Add new test for subgroups.Rafael Antognolli2019-07-232-0/+44
| | | | | | | | Make sure that a <group> tag within another <group> tag work just fine. v2: rename 'halfbyte' to 'byte' to match the size (Lionel). Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add basic infra for encoding/decoding unit tests.Rafael Antognolli2019-07-233-0/+145
| | | | | | | | Adding option to print quiet. v2: Add license header. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Decode <group> inside <group>.Rafael Antognolli2019-07-232-37/+93
| | | | | | | | | | Now we can decode a <group> tag inside another <group> tag, and properly print its indices and content. v2: Use push/pop stack to fields, groups and iters (Lionel). v3: Add assert(iter->level < DECODE_MAX_ARRAY_DEPTH) (Lionel). Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Add the concept of array "levels".Rafael Antognolli2019-07-232-9/+19
| | | | | | | We currently only support one level, which is the basic level of a <group> tag. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Add array field.Rafael Antognolli2019-07-232-3/+21
| | | | | | | | | | We currently use the group->next pointer to iterate through the <group> tags. This change them to be a type of field, so we can descend into them while iterating, and then go back to the original position. Will be useful when we want to decode <group>'s inside <group>'s, and when there are more <field>'s after a <group> tag. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Rename internally "group" to "array".Rafael Antognolli2019-07-232-25/+30
| | | | | | | | | | | | | A gen_group (group in most of the code) can be of several types: - instruction - struct - register - group (?!?) The <group> tag actually represents an array of elements. So at least in our code, lets call it an array to avoid confusion with gen_group. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Add gen_spec_load_filename() function.Rafael Antognolli2019-07-232-12/+21
| | | | | | | | | | Refactor the code from gen_spec_load_from_path() into a separate function, that can be used with a xml file that doesn't fit the genX.xml filename format. Will be used soon for implementing unit tests for gen_decoder. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/gen_decoder: Fix parsing of small genxml file.Rafael Antognolli2019-07-231-2/+6
| | | | | | | | | | | When using gen_spec_load_from path, only abort decoding if the read length is 0. Previously, we were aborting if finding an EOF, even if something was read from the file. Also only kill the decoded file if no commands or structs were found, and print a message in such case. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965,iris: Move guardband calculations to a common locationJason Ekstrand2019-06-212-0/+118
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Use get_state_size() over guessed counts in more casesKenneth Graunke2019-05-281-0/+2
| | | | | | | | | | | | | This makes the following packets use actual driver provided sizes rather than guessing an arbitrary number: - CC_VIEWPORT - SF_CLIP_VIEWPORT - BLEND_STATE - COLOR_CALC_STATE - SCISSOR_RECT Reviewed-by: Sagar Ghuge <[email protected]>
* intel/mi_builder: Disable mem_mem tests on IVBJason Ekstrand2019-04-161-0/+3
| | | | Tested-by: Clayton Craft <[email protected]>
* intel/mi_builder: Re-order an initializerJason Ekstrand2019-04-161-2/+2
| | | | | | The order doesn't matter in C99 but some C++ compilers seem to care. Tested-by: Clayton Craft <[email protected]>
* intel/common: Support bigger right-shifts with mi_builderJason Ekstrand2019-04-112-3/+20
| | | | Because why not?
* anv: Move mi_memcpy and mi_memset to gen_mi_builderJason Ekstrand2019-04-112-0/+75
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: Add unit tests for gen_mi_builderJason Ekstrand2019-04-112-0/+661
| | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/common: Add a MI command builderJason Ekstrand2019-04-111-0/+691
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/tools: Remove redundant definitions of INTEL_DEBUGMark Janes2019-04-101-2/+0
| | | | | | INTEL_DEBUG is declared extern and defined in gen_debug.c Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common: move gen_debug to intel/devMark Janes2019-04-103-246/+0
| | | | | | | | | libintel_common depends on libintel_compiler, but it contains debug functionality that is needed by libintel_compiler. Break the circular dependency by moving gen_debug files to libintel_dev. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: add dependency on genxml generated filesLionel Landwerlin2019-04-081-1/+1
| | | | | | | | | | Drivers using genxml will start compilation before generated files are created, so add a dependency to it. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Cc: [email protected]
* intel/decoders: silence uninitialized variable warnings in gen_print_batch()Brian Paul2019-03-081-2/+2
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoders: limit number of decoded batchbuffersLionel Landwerlin2019-03-072-2/+15
| | | | | | | | | | | IGT has a test to hang the GPU that works by having a batch buffer jump back into itself, trigger an infinite loop on the command stream. As our implementation of the decoding is "perfectly" mimicking the hardware, our decoder also "hangs". This change limits the number of batch buffer we'll decode before we bail to 100. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/decoders: handle decoding MI_BBS from ringLionel Landwerlin2019-03-072-4/+4
| | | | | | | | | An MI_BATCH_BUFFER_START in the ring buffer acts as a second level batchbuffer (aka jump back to ring buffer when running into a MI_BATCH_BUFFER_END). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/decoders: add address space indicator to get BOsLionel Landwerlin2019-03-072-15/+22
| | | | | | | Some commands like MI_BATCH_BUFFER_START have this indicator. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/debug: Add a debug flag to force software fp64Jason Ekstrand2019-03-062-1/+3
| | | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* drm-uapi: use local files, not system libdrmEric Engestrom2019-02-141-1/+1
| | | | | | | | | There was an issue recently caused by the system header being included by mistake, so let's just get rid of this include path and always explicitly #include "drm-uapi/FOO.h" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/batch-decoder: fix a vb end address calculationAndrii Simiklit2019-01-251-1/+3
| | | | | | | | | | According to the loop implementation (in 'ctx_print_buffer' function), which advances dword by dword over vertex buffer(vb), the vb size should be aligned by 4 bytes too. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109449 Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/batch-decoder: fix vertex buffer size calculation for gen<8Andrii Simiklit2019-01-251-1/+1
| | | | | | | | | | | | | | | | It should be incremented by one according to how it is calculated by 'emit_vertex_buffer_state': "\#if GEN_GEN < 8 .BufferAccessType = step_rate ? INSTANCEDATA : VERTEXDATA, .InstanceDataStepRate = step_rate, \#if GEN_GEN >= 5 .EndAddress = ro_bo(bo, end_offset - 1), \#endif \#endif" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109449 Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/icl: Set way_size_per_bank to 4Anuj Phogat2018-11-261-1/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/icl: Fix L3 configurationsAnuj Phogat2018-11-261-6/+6
| | | | | | | | | | Use L3 configuration specified in h/w specification. V2: Drop configs which do under allocation of l3 cache. Bump up the comment above table. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* intel/decoder: tools: Use engine for decoding batch instructionsToni Lönnberg2018-11-133-12/+26
| | | | | | | | | | | | | | | | The engine to which the batch was sent to is now set to the decoder context when decoding the batch. This is needed so that we can distinguish between instructions as the render and video pipe share some of the instruction opcodes. v2: The engine is now in the decoder context and the batch decoder uses a local function for finding the instruction for an engine. v3: Spec uses engine_mask now instead of engine, replaced engine class enums with the definitions from UAPI. v4: Fix up aubinator_viewer (Lionel) Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoder: Engine parameter for instructionsToni Lönnberg2018-11-132-0/+31
| | | | | | | | | | | | | | | | | | | Preliminary work for adding handling of different pipes to gen_decoder. Each instruction needs to have a definition describing which engine it is meant for. If left undefined, by default, the instruction is defined for all engines. v2: Changed to use the engine class definitions from UAPI v3: Changed I915_ENGINE_CLASS_TO_MASK to use BITSET_BIT, change engine to engine_mask, added check for incorrect engine and added the possibility to define an instruction to multiple engines using the "|" as a delimiter in the engine attribute. v4: Fixed the memory leak. v5: Removed an unnecessary ralloc_free(). Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/decoders: fix instruction base address parsingLionel Landwerlin2018-11-051-1/+1
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 00103db04ab879 ("intel: Fix decoding for partial STATE_BASE_ADDRESS updates.") Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use a URB start offset of 0 for disabled stages.Kenneth Graunke2018-11-031-3/+9
| | | | | | | | | | | | | | | | | | | | | | | There are some cases where the VS is the only stage enabled, it uses the entire URB, and the URB is large enough that placing later stages after the VS exceeds the number of bits for "URB Starting Address". For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from Piglit is getting a starting offset of 128 for the GS/HS/DS. But the field is only large enough to hold an offset of 127. i965 doesn't hit any genxml assertions because it's still using the old OUT_BATCH mechanism. 128 << GEN7_URB_STARTING_ADDRESS_SHIFT (57) == 0, with the extra bit falling off the end. So we place the disabled stage at the beginning of the URB (overlapping with push constants). This is likely okay since it's a zero size region (0 entries). It seems like the Vulkan driver might hit this assertion, however, and the situation seems harmless. To work around this, always place disabled stages at the start of the URB, so the last enabled stage can fill the remaining space without overflowing the field. Reviewed-by: Jordan Justen <[email protected]>
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