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* intel/tools: Decode PS kernels on SNBJason Ekstrand2019-09-061-1/+4
* intel/tools: Decode 3DSTATE_BINDING_TABLE_POINTERS on SNBJason Ekstrand2019-09-061-0/+15
* intel/gen12: Add L3 configurationsAnuj Phogat2019-09-061-1/+12
* intel/l3: Don't assert on gen12 (use gen11 config temporarily)Jordan Justen2019-08-281-0/+1
* intel/gen_decoder: Decode SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-0/+8
* meson,i965: Link with android deps when building for android.Bas Nieuwenhuizen2019-08-071-0/+10
* meson: drop unused dep_{thread,dl}Eric Engestrom2019-08-031-1/+1
* meson: replace libmesa_util with idep_mesautilEric Engestrom2019-08-031-3/+4
* intel/device: rename gen_get_device_infoMark Janes2019-08-011-1/+1
* intel/common: provide common ioctl routineMark Janes2019-08-011-0/+16
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
* intel/mi: only resolve to a temp register if source isn't in memoryEric Engestrom2019-07-291-1/+1
* intel/mi: Add a unit test for gen_mi_store_if().Kenneth Graunke2019-07-251-0/+43
* intel/mi: Add a new gen_mi_store_if() helper.Kenneth Graunke2019-07-251-0/+53
* intel/mi: Add gen_mi_nz() and gen_mi_z() helpers.Kenneth Graunke2019-07-251-0/+20
* intel/mi: Add a gen_mi_ior() to go with gen_mi_iand()Kenneth Graunke2019-07-251-0/+8
* intel/mi: Optimize away LOAD_REGISTER_REG from a register to itselfKenneth Graunke2019-07-251-3/+5
* intel/genxml: Add new test for subgroups.Rafael Antognolli2019-07-232-0/+44
* intel/genxml: Add basic infra for encoding/decoding unit tests.Rafael Antognolli2019-07-233-0/+145
* intel/gen_decoder: Decode <group> inside <group>.Rafael Antognolli2019-07-232-37/+93
* intel/gen_decoder: Add the concept of array "levels".Rafael Antognolli2019-07-232-9/+19
* intel/gen_decoder: Add array field.Rafael Antognolli2019-07-232-3/+21
* intel/gen_decoder: Rename internally "group" to "array".Rafael Antognolli2019-07-232-25/+30
* intel/gen_decoder: Add gen_spec_load_filename() function.Rafael Antognolli2019-07-232-12/+21
* intel/gen_decoder: Fix parsing of small genxml file.Rafael Antognolli2019-07-231-2/+6
* i965,iris: Move guardband calculations to a common locationJason Ekstrand2019-06-212-0/+118
* intel/decoder: Use get_state_size() over guessed counts in more casesKenneth Graunke2019-05-281-0/+2
* intel/mi_builder: Disable mem_mem tests on IVBJason Ekstrand2019-04-161-0/+3
* intel/mi_builder: Re-order an initializerJason Ekstrand2019-04-161-2/+2
* intel/common: Support bigger right-shifts with mi_builderJason Ekstrand2019-04-112-3/+20
* anv: Move mi_memcpy and mi_memset to gen_mi_builderJason Ekstrand2019-04-112-0/+75
* intel/common: Add unit tests for gen_mi_builderJason Ekstrand2019-04-112-0/+661
* intel/common: Add a MI command builderJason Ekstrand2019-04-111-0/+691
* intel/tools: Remove redundant definitions of INTEL_DEBUGMark Janes2019-04-101-2/+0
* intel/common: move gen_debug to intel/devMark Janes2019-04-103-246/+0
* intel: add dependency on genxml generated filesLionel Landwerlin2019-04-081-1/+1
* intel/decoders: silence uninitialized variable warnings in gen_print_batch()Brian Paul2019-03-081-2/+2
* intel/decoders: limit number of decoded batchbuffersLionel Landwerlin2019-03-072-2/+15
* intel/decoders: handle decoding MI_BBS from ringLionel Landwerlin2019-03-072-4/+4
* intel/decoders: add address space indicator to get BOsLionel Landwerlin2019-03-072-15/+22
* intel/debug: Add a debug flag to force software fp64Jason Ekstrand2019-03-062-1/+3
* drm-uapi: use local files, not system libdrmEric Engestrom2019-02-141-1/+1
* intel/batch-decoder: fix a vb end address calculationAndrii Simiklit2019-01-251-1/+3
* intel/batch-decoder: fix vertex buffer size calculation for gen<8Andrii Simiklit2019-01-251-1/+1
* intel/icl: Set way_size_per_bank to 4Anuj Phogat2018-11-261-1/+2
* i965/icl: Fix L3 configurationsAnuj Phogat2018-11-261-6/+6
* intel/decoder: tools: Use engine for decoding batch instructionsToni Lönnberg2018-11-133-12/+26
* intel/decoder: Engine parameter for instructionsToni Lönnberg2018-11-132-0/+31
* intel/decoders: fix instruction base address parsingLionel Landwerlin2018-11-051-1/+1
* intel: Use a URB start offset of 0 for disabled stages.Kenneth Graunke2018-11-031-3/+9
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