| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel: Use a URB start offset of 0 for disabled stages. | Kenneth Graunke | 2018-11-03 | 1 | -3/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | There are some cases where the VS is the only stage enabled, it uses the entire URB, and the URB is large enough that placing later stages after the VS exceeds the number of bits for "URB Starting Address". For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from Piglit is getting a starting offset of 128 for the GS/HS/DS. But the field is only large enough to hold an offset of 127. i965 doesn't hit any genxml assertions because it's still using the old OUT_BATCH mechanism. 128 << GEN7_URB_STARTING_ADDRESS_SHIFT (57) == 0, with the extra bit falling off the end. So we place the disabled stage at the beginning of the URB (overlapping with push constants). This is likely okay since it's a zero size region (0 entries). It seems like the Vulkan driver might hit this assertion, however, and the situation seems harmless. To work around this, always place disabled stages at the start of the URB, so the last enabled stage can fill the remaining space without overflowing the field. Reviewed-by: Jordan Justen <[email protected]> | ||||
| * | mesa: include mtypes.h less | Marek Olšák | 2018-04-12 | 1 | -0/+1 |
| | | | | | | | | | | | - remove mtypes.h from most header files - add main/menums.h for often used definitions - remove main/core.h v2: fix radv build Reviewed-by: Brian Paul <[email protected]> | ||||
| * | i965: Fix a mistake from porting the URB allocation code to arrays. | Kenneth Graunke | 2016-11-23 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | Commit 6d416bcd846a49414f210cd761789156c37a7b3e (i965: Use arrays in Gen7+ URB code.) introduced a regression which caused us to fail to allocate all of our URB space. - total_wants -= ds_wants; + total_wants -= additional; The new line should have been total_wants -= wants[i]. Fixes a large performance regression in TessMark. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98815 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> | ||||
| * | intel: Share URB configuration code between GL and Vulkan. | Kenneth Graunke | 2016-11-19 | 1 | -0/+201 |
| This code is far too complicated to cut and paste. v2: Update the newly added genX_gpu_memcpy.c; const a few things. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> | |||||
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