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* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-093-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b changed the shader_info from being embedded into being just a pointer. The idea was that sharing the shader_info between NIR and GLSL would be easier if it were a pointer pointing to the same shader_info struct. This, however, has caused a few problems: 1) There are many things which generate NIR without GLSL. This means we have to support both NIR shaders which come from GLSL and ones that don't and need to have an info elsewhere. 2) The solution to (1) raises all sorts of ownership issues which have to be resolved with ralloc_parent checks. 3) Ever since 00620782c92100d77c660f9783504c6d80fa1d58, we've been using nir_gather_info to fill out the final shader_info. Thanks to cloning and the above ownership issues, the nir_shader::info may not point back to the gl_shader anymore and so we have to do a copy of the shader_info from NIR back to GLSL anyway. All of these issues go away if we just embed the shader_info in the nir_shader. There's a little downside of having to copy it back after calling nir_gather_info but, as explained above, we have to do that anyway. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.Rafael Antognolli2017-05-031-2/+2
| | | | | | | | | - "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Normalize xml for 3DSTATE_MULTISAMPLE.Rafael Antognolli2017-05-031-3/+1
| | | | | | | | | Name the options to "Pixel Location": - PIXLOC_CENTER -> CENTER - PIXLOC_UL_CORNER -> UL_CORNER Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: 3DSTATE_VS rename Function Enable to Enable.Rafael Antognolli2017-05-031-1/+1
| | | | | Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-241-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand2017-04-141-64/+50
| | | | | | | This makes it much easier to throw together a bit of dynamic state. It also automatically handles flushing so you don't accidentally forget. Reviewed-by: Alejandro Piñeiro <[email protected]>
* intel/blorp: Use ISL for emitting depth/stencil/hizJason Ekstrand2017-04-101-86/+33
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTHJason Ekstrand2017-04-101-12/+12
| | | | | | | We're about to replace blorp's emit code with ISL and it emits them in the other order. This makes diffing the aubs easier. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel: Fix requests for exact surface row pitch (v2)Chad Versace2017-03-281-3/+5
| | | | | | | | | | | | | | All callers of isl_surf_init() that set 'min_row_pitch' wanted to request an *exact* row pitch, as evidenced by nearby asserts, but isl lacked API for doing so. Now that isl has an API for that, update the code to use it. v2: Assert that isl_surf_init() succeeds because the callers assume it. [for jekstrand] Reviewed-by: Nanley Chery <[email protected]> (v1) Reviewed-by: Anuj Phogat <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* i965: Drop AUB_TRACE_* stuff.Kenneth Graunke2017-03-211-7/+5
| | | | | | | | | | | | This was used for aubdumping (deleted a while ago) and INTEL_DEBUG=bat decoding (deleted recently). While we're changing parameters, delete the wrapper macro and make the actual function brw_state_batch instead of __brw_state_batch. This subsumes a patch by Emil Velikov to drop this from BLORP. Reviewed-by: Emil Velikov <[email protected]>
* anv: avoid crashes when failing to allocate batchesIago Toral Quiroga2017-03-161-8/+17
| | | | | | | | | | | | | | | | | | | | | | Most of the time we use macros that handle this situation transparently, but there are some cases were we need to handle this explicitly. This patch makes sure we don't crash, notice that error handling takes place in the function that actually failed the allocation, anv_batch_emit_dwords(), which will set the status field of the batch so it can be used at a later moment to report the error to the user. v2: - Not crashing is not good enough, we need to keep track of the error (Topi, Jason). Iago: now that we track errors in the batch, this is being handled. - Added guards in a few more places that needed it (Iago) v3: - Check result of anv_batch_emitn() for NULL before calling memset() in emit_vertex_input() (Topi) Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: make upload_shader() return a bool indicating success or failureIago Toral Quiroga2017-03-163-26/+39
| | | | | | For now we always return true, follow-up patches will handle fail scenarios. Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: Rework conversion opcodesJason Ekstrand2017-03-141-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | The NIR story on conversion opcodes is a mess. We've had way too many of them, naming is inconsistent, and which ones have explicit sizes was sort-of random. This commit re-organizes things and makes them all consistent: - All non-bool conversion opcodes now have the explicit size in the destination and are named <src_type>2<dst_type><size>. - Integer <-> integer conversion opcodes now only come in i2i and u2u forms (i2u and u2i have been removed) since the only difference between the different integer conversions is whether or not they sign-extend when up-converting. - Boolean conversion opcodes all have the explicit size on the bool and are named <src_type>2<dst_type>. Making things consistent also allows nir_type_conversion_op to be moved to nir_opcodes.c and auto-generated using mako. This will make adding int8, int16, and float16 versions much easier when the time comes. Reviewed-by: Eric Anholt <[email protected]>
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-133-4/+4
| | | | | | | | | | | | | | | | | | | | | | Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | Split out the EU defines from the 'generic' ones, as the former are more compiler oriented. With a later commit we'll move brw_eu_defines.h alongside the compiler infra to src/intel/. Pulling all the defines in there seems overzealous. Some defines are used by both i965 and the i965 compiler. Those are moved to brw_eu_defines.h, and annotated accordingly. The i965 users were updated to have the extre include to indicate that. With future work we might provide a better, split but for now this seems reasonable. Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Reduce cross-pollination between the DRI driver and compilerJason Ekstrand2017-03-011-1/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Explicitly flush all allocated stateJason Ekstrand2017-02-211-1/+18
| | | | | | | | Found by inspection. However, I expect it fixes real bugs when using blorp from Vulkan on little-core platforms. Reviewed-by: Lionel Landwerlin <[email protected]> Cc: "13.0 17.0" <[email protected]>
* intel/blorp: Swizzle clear colors on the CPUJason Ekstrand2017-02-131-18/+30
| | | | | | | | | It's trivial to swizzle clear colors on the CPU, easily deals with the hardware restrictions for render target swizzles, and makes swizzled clears work on all hardware as opposed to just HSW+. Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: "17.0" <[email protected]>
* intel/blorp: do not return const data by get_px_size_sa()Emil Velikov2017-02-101-1/+1
| | | | | | | | | | | | | Not much point in the const qualifier since we provide a copy to the user. Resolves the following -Wignored-qualifiers warning. src/intel/blorp/blorp_blit.c:1857:8: warning: 'const' type qualifier on return type has no effect [-Wignored-qualifiers] v2: keep const qualifier of local variable. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add a formats_are_ccs_e_compatible helperJason Ekstrand2017-02-021-0/+6
| | | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* intel/blorp: Handle clearing of A4B4G4R4 on all platformsJason Ekstrand2017-01-311-0/+23
| | | | | | Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* intel/blorp/dbg: Name blit shaders for easy recognition in dumpsTopi Pohjolainen2017-01-271-0/+2
| | | | | | | | Blorp clears already have an equivalent. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/blorp/copy: Properly handle clear colors for CCS_E imagesJason Ekstrand2017-01-211-0/+82
| | | | | | | | | | | | | | In order to handle CCS_E, we stomp the image format to a UINT format and then do some bitcasting logic in the shader. This works fine since SKL render compression only considers the channel layout of the format and not the format itself. In order for this to work on images that have been fast-cleared, we need to also convert the clear color so that, when interpreted as UINT, it provides the same bit value as it would have in the original format. This fixes a bunch of OpenGL ES CTS tests for copy_image when we start using CCS more aggressively. Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "17.0" <[email protected]>
* blorp: remove unnecessary struct declarationLionel Landwerlin2017-01-201-1/+0
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_clear: Add gen8 HiZ clearing functionsNanley Chery2017-01-122-0/+93
| | | | | | | | | | | | | Add an entry point for the optimized gen8 BLORP HiZ sequence. commit c9eaf12de20ac4143fe79d42018bdbb5a391356f fixed a bug that was unknowingly worked around by forcing additional clear rectangle alignment restrictions not specified in the PRMs. Now that the bug is no longer present, omit the additional alignment restrictions. v2: Adjust code comment about padding Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORPNanley Chery2017-01-121-0/+87
| | | | | | | | | | | We'll be switching to layout-transition based resolves which can occur outside of a render pass. Add this sequence to BLORP, as using BLORP will enable emitting depth stencil state outside of a render pass (among other benefits). The depth buffer extent is ignored to enable eventual usage in VkCmdClearAttachments(). Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Fix max blit size for gen6Jordan Justen2016-12-261-2/+3
| | | | | | | | Fixes ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp_blit: Add split_blorp_blit_debug switchJordan Justen2016-12-071-3/+9
| | | | | | | | | Enabling this debug switch causes surface shrinking to happen by default, and lowers the surface size limit which causes blorp blits to be split. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Enable splitting large blorp blitsJordan Justen2016-12-071-1/+40
| | | | | | | | | | | | | | | | Detect when the surface sizes are too large for a blorp blit. When it is too large, the blorp blit will be split into a smaller operation and attempted again. For gen7, this fixes the cts test: ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit It will also enable us to increase our renderable size from 8k x 8k to 16k x 16k. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Move RGB=>R conversion to follow blit splittingJordan Justen2016-12-071-48/+65
| | | | | | | | | | | | | | In blorp_copy, when RGB surfaces are copied, we convert the destination surface to a Red only surface, but 3 times as wide. This introduces an implicit restriction of "mod 3" for the destination width. It is easier to handle the blorp split buffer offsetting with the original RGB surface, and do the RGB=>R after this. Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Adjust blorp surface parameters for split blitsJordan Justen2016-12-071-3/+94
| | | | | | | | | | | | If try_blorp_blit() previously returned that a blit was too large, shrink_surface_params() will be used to update the surface parameters for the smaller blit so the blit operation can proceed. v2: * Use double instead of float. (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Split blorp blits if they are too largeJordan Justen2016-12-071-6/+96
| | | | | | | | | | | | | | | | | | | | | We rename do_blorp_blit() to try_blorp_blit(), and add a return error if the surface size for the blit is too large. Now, do_blorp_blit() is rewritten to try to split the blit into smaller operations if try_blorp_blit() fails. Note: In this commit, try_blorp_blit() will always attempt to blit and never return an error, which matches the previous behavior. We will enable the size checking and splitting in a future commit. The motivation for this splitting is that in some cases when we flatten an image, it's dimensions grow, and this can then exceed the programmable hardware limits. An example is w-tiled+MSAA blits. v2: * Use double instead of float. (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp_blit: Create structure for src & dst coordinatesJordan Justen2016-12-071-19/+56
| | | | | | | | | | | | | | This will be useful for splitting blits into smaller sizes. We also make the coordinates of type double rather than float. Since we will be splitting and scaling the coordinates, we might require extra precision in the calculations. v2: * Use double instead of float. (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Fix rectangle size for level-not-zero resolvesTopi Pohjolainen2016-11-231-2/+2
| | | | | | | | Needed to prevent gpu hangs when mip-mapped compression gets enabled. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Properly handle color compression in blorp_copyJason Ekstrand2016-11-172-2/+179
| | | | | | | | | Previously, blorp copy operations were CCS-unaware so you had to perform resolves on the source and destination before performing the copy. This commit makes blorp_copy capable of handling CCS-compressed images without any resolves. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Always use UINT formats on SKL+Jason Ekstrand2016-11-171-22/+44
| | | | | | | | | Many of these UINT formats aren't available prior to Sky Lake so we used UNORM formats. Using UINT formats is a bit nicer because it guarantees we don't run into rounding issues. Also, we will need it in the next commit for handling copies with CCS enabled. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Take a fast_clear_op in ccs_resolveJason Ekstrand2016-11-173-14/+15
| | | | | | | | Eventually, we may want to just have a single blorp_ccs_op function that does both clears and resolves. For now we'll stick to just making the ccs_resolve function we have now a bit more configurable. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add plumbing for color resolve slice detailsPohjolainen, Topi2016-11-172-3/+9
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Add a clear_attachments entrypointJason Ekstrand2016-11-163-2/+173
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add capability to use pre-baked binding tablesJason Ekstrand2016-11-162-20/+27
| | | | | | | | | When a pre-baked binding table is requested, no binding table is created, instead the binding table offset (relative to surface state base address) provided by the user is used verbatim. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add support for vertex shadersJason Ekstrand2016-11-163-6/+82
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Use an actual chunk of vertex buffer for the VUE headerJason Ekstrand2016-11-161-33/+34
| | | | | | | | | | | We're about to start passing other things in as a sort of "VS header" for vertex shaders and we need a place to put them. Since we want the instance id to be one of them, it makes sense to have one vec4 that's either VUE header or VS header. Always uploading some handy zeros makes the code a bit simpler. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* blorp/exec: Use uint32_t for copying varying dataJason Ekstrand2016-11-161-2/+2
| | | | | | | | Some things may not be floats and intel CPUs are known for mangling bits when a float type is used for copying integers. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Handle NIR clear inputs the same way as blit inputsJason Ekstrand2016-11-163-11/+17
| | | | | | | | By using offsetof() we can ensure that adding fiels to wm_inputs is always safe as long as we maintain alignment. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Remove NIR support for uniformsJason Ekstrand2016-11-161-23/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add a shader type to make keys more uniqueJason Ekstrand2016-11-163-7/+18
| | | | | | | | | | Depending on how the driver using blorp implements its shader caching, there is a small chance of shader collisions due to identical keys between blit and clear programs. Adding a small shader type at the top of the key alleviates this problem. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make the number of samples an explicit parameterJason Ekstrand2016-11-165-9/+19
| | | | | | | | | Previously, we always inferred it from params->dst which meant that references to params->dst were scattered all throughout the state upload code. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add some basic info about RENDER_SURFACE_STATE to isl_deviceJason Ekstrand2016-11-161-24/+9
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/genxml: Make 3DSTATE_WM more consistent across gensJason Ekstrand2016-11-161-2/+2
| | | | | Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* intel/genxml: Make some 3DSTATE_PS fields more consistentJason Ekstrand2016-11-161-4/+4
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
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