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* blorp: Use normalized coordinates on Gen6Ian Romanick2017-06-262-5/+8
| | | | | | | | | | | | | | Apparently, the sampler has some sort of precision issues for non-normalized texture coordinates with linear filtering. This caused some small precision issues in scaled blits. Work around this by using normalized coordinates. There is some extra work necessary because Gen6 uses TEX (instead of TXF) for some multisample resolve blits. Fixes piglit.spec.arb_framebuffer_object.fbo-blit-stretch on SNB. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68365 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* blorp/clear: Add a binding-table-based CCS resolve functionNanley Chery2017-06-262-17/+57
| | | | | | | | | | | | | v2: - Do layered resolves. (Jason Ekstrand): - Replace "bt" suffix with "attachment". - Rename helper function to prepare_ccs_resolve. - Move blorp_params_init() into helper function. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Check for layer fast-clear restrictionNanley Chery2017-06-261-0/+5
| | | | | | | | v2: Update commit title (Jason Ekstrand) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Assert levels and layers are in rangeNanley Chery2017-06-262-4/+7
| | | | | | | | | | | | v2 (Jason Ekstrand): - Update commit title. - Check aux level and layer as well. v3 (Jason Ekstrand): - Move the non-aux layer check. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Apply source offset in the TEX caseIan Romanick2017-06-201-0/+3
| | | | | | | | Previously the offset was only applied in the TXF case. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjustedIan Romanick2017-06-201-9/+11
| | | | | | | | | Otherwise the values used for coordinate normalization use the wrong sizes. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Jason Ekstrand <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemapsJason Ekstrand2017-06-201-2/+6
| | | | | | | | | | | | | | | We call convert_to_single_slice so they may end up with a non-trivial offset that needs to be taken into account. v2 (idr): Also set needs_src_offset. Suggested by Jason. Fixes ES2-CTS.functional.texture.specification.basic_copyteximage2d.cube_rgba and ES2-CTS.functional.texture.specification.basic_copytexsubimage2d.cube_rgba on G45. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101284 Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* blorp: Use FullSurfaceDepthandStencilClear for blorp_hiz_opJason Ekstrand2017-06-073-0/+5
| | | | | | | The blorp_hiz_op entrypoint always acts on a full subresource of a HiZ buffer so we can just set the flag unconditionally. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Plumb through access to the workaround BOJason Ekstrand2017-06-071-2/+7
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101283 Reviewed-by: Topi Pohjolainen <[email protected]>
* anv/blorp: Move the depth cache flush outside of BLORPNanley Chery2017-06-071-8/+0
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Refactor the HiZ op interfaceJason Ekstrand2017-06-072-52/+58
| | | | | | | | | | This commit does a few things: 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix. 2) Switch parameters to uint32_t to match the rest of blorp. 3) Take a range of layers and loop internally. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This commit, out of necessity, makes a number of changes at once: 1) Changes intel_mipmap_tree to store the clear color for both color and depth as an isl_color_value. 2) Changes the depth/stencil emit code to do the format conversion of the depth clear value on Haswell and earlier instead of pulling a uint32_t directly from the miptree. 3) Changes ISL's depth/stencil emit code to perform the format conversion of the depth clear value on Haswell and earlier instead of assuming that the depth value in the float is pre-converted. 4) Changes blorp to pass the depth value through as a float. 5) Changes the Vulkan driver to pass the depth value to blorp as a float rather than a uint. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-011-2/+30
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a helper for getting the byte/tile offset of a subimageJason Ekstrand2017-06-011-9/+4
| | | | | | | | | Frequently, get_image_offset_sa is combined with get_intratile_offset_sa so it makes sense to have a single helper to do both. If the caller doesn't want the intratile offsets, it can simply pass NULL and ISL will assert that they are 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-011-2/+2
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use BLORP for color clears on gen4-5Jason Ekstrand2017-05-261-0/+4
| | | | | | | | We don't support replicated data clears yet. Those take a bit more work and enabling replicated data clears in its own commit is probably better for bisectibility anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Assert that no one tries to blit combined depth stencilJason Ekstrand2017-05-261-0/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add blorp support for gen4-5Jason Ekstrand2017-05-264-12/+95
| | | | | | | | | | Due to complications with things such as URB setup on gen4-5, it's easier to keep gen4 support in blorp completely internal to i965. This makes things a bit awkward because that means there's a file in i965 that includes blorp_priv.h but it's either that or have a file in blorp that includes brw_context.h. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Set additional brw_wm_prog_key fields on gen4-5Jason Ekstrand2017-05-262-2/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add support for gen4-5 SF programsJason Ekstrand2017-05-265-2/+81
| | | | | | | | As part of enabling support for SF programs, we plumb the SF URB size through to emit_urb_config. For now, it's always zero but, on gen4, it may be something larger. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make convert_to_single_slice available outside blorp_blitJason Ekstrand2017-05-262-8/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Use designated initializers to set up VERTEX_ELEMENTSJason Ekstrand2017-05-261-32/+43
| | | | | | | | We also add a slot variable and use it as an iterator. This will make it much easier to conditionally put something between the header and the vertex position. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Rename emit_viewport_state to emit_cc_viewportJason Ekstrand2017-05-261-3/+3
| | | | | | | The real point of this packet is that it sets up CC_VIEWPORT so that name is a bit better. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Make the common genX_blorp_exec code gen4-safeJason Ekstrand2017-05-261-8/+36
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Re-arrange blorp_genX_exec.hJason Ekstrand2017-05-261-229/+229
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Don't use ffma directlyJason Ekstrand2017-05-261-1/+1
| | | | | | | It isn't supported prior to gen6 and, on gen6+, NIR will fuse the fmul and fadd into an ffma automatically for us anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Delete isl_to_gen_ds_surfypeJason Ekstrand2017-05-261-19/+0
| | | | | | It's no longer used. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Pull the pipeline bits of blorp_exec into a helperJason Ekstrand2017-05-261-25/+31
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp/blit: Add support for normalized coordinatesJason Ekstrand2017-05-262-5/+28
| | | | | | | Gen5 and earlier can't do non-normalized coordinates so we need to compensate in the shader. Fortunately, it's pretty easy plumb through. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Move the gen7 stencil format workaround to blorp_blitJason Ekstrand2017-05-262-5/+9
| | | | | | | | It's not needed for blorp_copy because it already overrides formats. It's also not needed for blorp_clear because it clears stencil as stencil. Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-093-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b changed the shader_info from being embedded into being just a pointer. The idea was that sharing the shader_info between NIR and GLSL would be easier if it were a pointer pointing to the same shader_info struct. This, however, has caused a few problems: 1) There are many things which generate NIR without GLSL. This means we have to support both NIR shaders which come from GLSL and ones that don't and need to have an info elsewhere. 2) The solution to (1) raises all sorts of ownership issues which have to be resolved with ralloc_parent checks. 3) Ever since 00620782c92100d77c660f9783504c6d80fa1d58, we've been using nir_gather_info to fill out the final shader_info. Thanks to cloning and the above ownership issues, the nir_shader::info may not point back to the gl_shader anymore and so we have to do a copy of the shader_info from NIR back to GLSL anyway. All of these issues go away if we just embed the shader_info in the nir_shader. There's a little downside of having to copy it back after calling nir_gather_info but, as explained above, we have to do that anyway. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.Rafael Antognolli2017-05-031-2/+2
| | | | | | | | | - "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Normalize xml for 3DSTATE_MULTISAMPLE.Rafael Antognolli2017-05-031-3/+1
| | | | | | | | | Name the options to "Pixel Location": - PIXLOC_CENTER -> CENTER - PIXLOC_UL_CORNER -> UL_CORNER Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: 3DSTATE_VS rename Function Enable to Enable.Rafael Antognolli2017-05-031-1/+1
| | | | | Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-241-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand2017-04-141-64/+50
| | | | | | | This makes it much easier to throw together a bit of dynamic state. It also automatically handles flushing so you don't accidentally forget. Reviewed-by: Alejandro Piñeiro <[email protected]>
* intel/blorp: Use ISL for emitting depth/stencil/hizJason Ekstrand2017-04-101-86/+33
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTHJason Ekstrand2017-04-101-12/+12
| | | | | | | We're about to replace blorp's emit code with ISL and it emits them in the other order. This makes diffing the aubs easier. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel: Fix requests for exact surface row pitch (v2)Chad Versace2017-03-281-3/+5
| | | | | | | | | | | | | | All callers of isl_surf_init() that set 'min_row_pitch' wanted to request an *exact* row pitch, as evidenced by nearby asserts, but isl lacked API for doing so. Now that isl has an API for that, update the code to use it. v2: Assert that isl_surf_init() succeeds because the callers assume it. [for jekstrand] Reviewed-by: Nanley Chery <[email protected]> (v1) Reviewed-by: Anuj Phogat <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]> (v2)
* i965: Drop AUB_TRACE_* stuff.Kenneth Graunke2017-03-211-7/+5
| | | | | | | | | | | | This was used for aubdumping (deleted a while ago) and INTEL_DEBUG=bat decoding (deleted recently). While we're changing parameters, delete the wrapper macro and make the actual function brw_state_batch instead of __brw_state_batch. This subsumes a patch by Emil Velikov to drop this from BLORP. Reviewed-by: Emil Velikov <[email protected]>
* anv: avoid crashes when failing to allocate batchesIago Toral Quiroga2017-03-161-8/+17
| | | | | | | | | | | | | | | | | | | | | | Most of the time we use macros that handle this situation transparently, but there are some cases were we need to handle this explicitly. This patch makes sure we don't crash, notice that error handling takes place in the function that actually failed the allocation, anv_batch_emit_dwords(), which will set the status field of the batch so it can be used at a later moment to report the error to the user. v2: - Not crashing is not good enough, we need to keep track of the error (Topi, Jason). Iago: now that we track errors in the batch, this is being handled. - Added guards in a few more places that needed it (Iago) v3: - Check result of anv_batch_emitn() for NULL before calling memset() in emit_vertex_input() (Topi) Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: make upload_shader() return a bool indicating success or failureIago Toral Quiroga2017-03-163-26/+39
| | | | | | For now we always return true, follow-up patches will handle fail scenarios. Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: Rework conversion opcodesJason Ekstrand2017-03-141-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | The NIR story on conversion opcodes is a mess. We've had way too many of them, naming is inconsistent, and which ones have explicit sizes was sort-of random. This commit re-organizes things and makes them all consistent: - All non-bool conversion opcodes now have the explicit size in the destination and are named <src_type>2<dst_type><size>. - Integer <-> integer conversion opcodes now only come in i2i and u2u forms (i2u and u2i have been removed) since the only difference between the different integer conversions is whether or not they sign-extend when up-converting. - Boolean conversion opcodes all have the explicit size on the bool and are named <src_type>2<dst_type>. Making things consistent also allows nir_type_conversion_op to be moved to nir_opcodes.c and auto-generated using mako. This will make adding int8, int16, and float16 versions much easier when the time comes. Reviewed-by: Eric Anholt <[email protected]>
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-133-4/+4
| | | | | | | | | | | | | | | | | | | | | | Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | Split out the EU defines from the 'generic' ones, as the former are more compiler oriented. With a later commit we'll move brw_eu_defines.h alongside the compiler infra to src/intel/. Pulling all the defines in there seems overzealous. Some defines are used by both i965 and the i965 compiler. Those are moved to brw_eu_defines.h, and annotated accordingly. The i965 users were updated to have the extre include to indicate that. With future work we might provide a better, split but for now this seems reasonable. Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Reduce cross-pollination between the DRI driver and compilerJason Ekstrand2017-03-011-1/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Explicitly flush all allocated stateJason Ekstrand2017-02-211-1/+18
| | | | | | | | Found by inspection. However, I expect it fixes real bugs when using blorp from Vulkan on little-core platforms. Reviewed-by: Lionel Landwerlin <[email protected]> Cc: "13.0 17.0" <[email protected]>
* intel/blorp: Swizzle clear colors on the CPUJason Ekstrand2017-02-131-18/+30
| | | | | | | | | It's trivial to swizzle clear colors on the CPU, easily deals with the hardware restrictions for render target swizzles, and makes swizzled clears work on all hardware as opposed to just HSW+. Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: "17.0" <[email protected]>
* intel/blorp: do not return const data by get_px_size_sa()Emil Velikov2017-02-101-1/+1
| | | | | | | | | | | | | Not much point in the const qualifier since we provide a copy to the user. Resolves the following -Wignored-qualifiers warning. src/intel/blorp/blorp_blit.c:1857:8: warning: 'const' type qualifier on return type has no effect [-Wignored-qualifiers] v2: keep const qualifier of local variable. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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