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* intel/blorp: Plumb the stage through blorp upload_shaderCaio Marcelo de Oliveira Filho2020-03-171-3/+6
| | | | | | | | | | Vulkan uses that for its own upload function -- even though for BLORP it doesn't really currently care. Neither Iris and i965 makes use of it at the moment. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
* iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZJason Ekstrand2020-03-121-1/+1
| | | | | | | | | | | | | Previously, we always set the aux_usage to ISL_AUX_USAGE_HIZ_CCS and let ISL choose write-through based on isl_surf_supports_hiz_ccs_wt. This commit makes us choose explicitly at surface creation time whether to use HIZ_CCS or HIZ_CCS_WT based on the same set of conditions. This is more explicit and should be more robust as it lets us choose WT mode in one place rather than trusting isl_surf_supports_hiz_ccs_wt to return the same thing every time. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
* intel/blorp: Fix usage of uninitialized memory in key hashingDanylo Piliaiev2019-11-121-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The automatically generated padding in structs contains undefined values, force pack the structs to eliminate the padding. Otherwise structs with the same values may generate different hashes. Valgrind output: Conditional jump or move depends on uninitialised value(s) util_fast_urem32 (fast_urem_by_const.h:71) hash_table_search (hash_table.c:262) _mesa_hash_table_search (hash_table.c:296) anv_pipeline_cache_search_locked (anv_pipeline_cache.c:318) anv_pipeline_cache_search (anv_pipeline_cache.c:335) lookup_blorp_shader (anv_blorp.c:38) blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1112) blorp_mcs_partial_resolve (blorp_clear.c:1205) anv_image_mcs_op (anv_blorp.c:1742) anv_cmd_predicated_mcs_resolve (genX_cmd_buffer.c:774) transition_color_buffer (genX_cmd_buffer.c:1159) cmd_buffer_end_subpass (genX_cmd_buffer.c:4840) Uninitialised value was created by a stack allocation blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1103) Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* Revert "intel/blorp: Fix usage of uninitialized memory in key hashing"Kenneth Graunke2019-11-071-6/+1
| | | | | | | This reverts commit 4432a2d14d80081d062f7939a950d65ea3a16eed. Pretty much every SKQP test dies with this assertion: skqp: ../src/mesa/drivers/dri/i965/brw_program_cache.c:102: hash_key: Assertion `item->key_size % 4 == 0' failed.
* intel/blorp: Fix usage of uninitialized memory in key hashingDanylo Piliaiev2019-11-071-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The automatically generated padding in structs contains undefined values, force pack the structs to eliminate the padding. Otherwise structs with the same values may generate different hashes. Valgrind output: Conditional jump or move depends on uninitialised value(s) util_fast_urem32 (fast_urem_by_const.h:71) hash_table_search (hash_table.c:262) _mesa_hash_table_search (hash_table.c:296) anv_pipeline_cache_search_locked (anv_pipeline_cache.c:318) anv_pipeline_cache_search (anv_pipeline_cache.c:335) lookup_blorp_shader (anv_blorp.c:38) blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1112) blorp_mcs_partial_resolve (blorp_clear.c:1205) anv_image_mcs_op (anv_blorp.c:1742) anv_cmd_predicated_mcs_resolve (genX_cmd_buffer.c:774) transition_color_buffer (genX_cmd_buffer.c:1159) cmd_buffer_end_subpass (genX_cmd_buffer.c:4840) Uninitialised value was created by a stack allocation blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1103) Cc: <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/blorp: Assign correct view while clearing depth stencilSagar Ghuge2019-10-291-1/+1
| | | | | | | | | | We never saw any failures regarding this typo but it's good to assign correct stencil view while constructing blorp_params. Fixes: 0cabf93b80d0 "intel/blorp: Add an entrypoint for clearing depth and stencil" Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Satisfy HIZ_CCS fast-clear alignmentsNanley Chery2019-10-281-0/+47
| | | | | | | | Prevent the piglit test, amd_vertex_shader_layer-layered-depth-texture-render, from regressing in in a future commit. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Refactor blorp_can_hiz_clear_depth()Nanley Chery2019-10-281-6/+9
| | | | | | | Prepare this function to be used in iris and to handle new Gen12 behavior. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Don't assert aux slices match main slicesNanley Chery2019-10-281-5/+0
| | | | | | | | | This isn't accurate enough for HiZ which can have a discontiguous range of supported aux slices. This also won't work with the plan to represent Gen12 CCS as a single slice surface. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Use surf instead of aux_surf for image dimensionsJason Ekstrand2019-10-281-2/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Halve the Gen12 fast-clear/resolve rectangleNanley Chery2019-10-281-4/+9
| | | | | | | Update their dimensions according to the Bspec. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Use wide formats for nicely aligned stencil clearsJason Ekstrand2019-09-061-0/+108
| | | | | | | | | | | | | | | | In the case where the stencil clear is nicely aligned, we can clear stencil much more efficiently by mapping it as a wide format (say RGBA32_UINT) and blasting out the stencil clear value with a repclear. On Unigine Heaven, this makes one stencil clear go from non-trivial to unnoticeable when looking at per-draw timings. In order for this change to work properly, ANV needs to do a bit more flushing around depth and stencil clears. i965 and iris already have the cache tracking logic to handle this so no changes are required there. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
| | | | | | Suggested-by: Jason Ekstrand <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Use a system value for gl_FragCoordJason Ekstrand2019-07-291-7/+2
| | | | | | | | | | | | It's kind-of an anomaly that the Intel drivers are still treating gl_FragCoord as an input. It also makes zero sense because we have to special-case it in the back-end. Because ANV is the only user of nir_lower_wpos_center, we go ahead and just update it to look for nir_intrinsic_load_frag_coord as part of this patch. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Add a "base class" for program keysJason Ekstrand2019-07-101-2/+2
| | | | | | | | | Right now, all keys have two things in common: a program string ID and a sampler_prog_key_data. I'd like to add another thing or two and need a place to put it. This commit adds a new brw_base_prog_key struct which contains those two common bits. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Only double the fast-clear rect alignment on HSWJason Ekstrand2019-06-071-10/+15
| | | | | | | | | This restriction was accidentally added to the BSpec/PRM as an unrestricted restriction starting with the HSW docs and it was never removed. However, it only ever applied to HSW and actually potentially causes problems on BDW and above where we have mipmapped fast-clears. Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Use the hardware op for CCS ambiguate on gen10+Jason Ekstrand2019-05-301-1/+11
| | | | | | | | | | Cannonlake hardware adds a new resolve type in 3DSTATE_PS called FAST_CLEAR_0 which does an ambiguate. Now that the hardware can do it directly, we should use that instead of binding the CCS as a render target and doing it manually. This was tested with a full Vulkan CTS run on Cannonlake. Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Make swizzle_color_value public.Rafael Antognolli2019-03-201-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir, glsl: move pixel_center_integer/origin_upper_left to shader_info.fsAlejandro Piñeiro2019-02-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On GLSL that info is set as a layout qualifier when redeclaring gl_FragCoord, so somehow tied to a specific variable. But in practice, they behave as a global of the shader. On ARB programs they are set using a global OPTION (defined at ARB_fragment_coord_conventions), and on SPIR-V using ExecutionModes, that are also not tied specifically to the builtin. This patch moves that info from nir variable and ir variable to nir shader and gl_program shader_info respectively, so the map is more similar to SPIR-V, and ARB programs, instead of more similar to GLSL. FWIW, shader_info.fs already had pixel_center_integer, so this change also removes some redundancy. Also, as struct gl_program also includes a shader_info, we removed gl_program::OriginUpperLeft and PixelCenterInteger, as it would be superfluous. This change was needed because recently spirv_to_nir changed the order in which execution modes and variables are handled, so the variables didn't get the correct values. Now the info is set on the shader itself, and we don't need to go back to the builtin variable to set it. Fixes: e68871f6a ("spirv: Handle constants and types before execution modes") v2: (Jason) * glsl_to_nir: get the info before glsl_to_nir, while all the rest of the info gathering is happening * prog_to_nir: gather the info on a general info-gathering pass, not on variable setup. v3: (Jason) * Squash with the patch that removes that info from ir variable * anv: assert that OriginUpperLeft is true. It should be already set by spirv_to_nir. * blorp: set origin_upper_left on its core "compile fragment shader", not just on some specific places (for this we added an helper on a previous patch). * prog_to_nir: no need to gather specifically this fragcoord modes as the full gl_program shader_info is copied. * spirv_to_nir: assert that we are a fragment shader when handling this execution modes. v4: (reported by failing gitlab pipeline #18750) * state_tracker: update too due changes on ir.h/gl_program v5: * blorp: minor change after change on previous patch * radeonsi: update due this change. v6: (Timothy Arceri) * prog_to_nir: remove extra whitespace * shader_info: don't use :1 on origin_upper_left * glsl: program.fs.origin_upper_left/pixel_center_integer can be move out of the shader list loop
* blorp: introduce helper method blorp_nir_init_shaderAlejandro Piñeiro2019-02-211-6/+4
| | | | | | | | This initializes the nir shader that will be used by blorp. Right now it doesn't do too much beyond calling nir_builder_init_simple_shader, and setting a name. More stuff will be added on following patches. v2: there is a case were it is used a VERTEX_SHADER (Alejandro)
* blorp: Pass the batch to lookup/upload_shader instead of contextKenneth Graunke2019-01-101-18/+22
| | | | | | | | | This will allow drivers to pin shader buffers if necessary. i965 and anv do not need to do this today, but iris will. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand2018-09-261-2/+2
| | | | | | | | | | | | | I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Handle 3-component formats in clearsJason Ekstrand2018-07-131-10/+88
| | | | | | | | This fixes a nasty hang in Batman: Arkham City which apparently calls vkCmdClearColorImage on a linear RGB image. cc: [email protected] Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/blorp: Support blits and clears on surfaces with offsetsJason Ekstrand2018-05-251-0/+9
| | | | | | | | | | | | | For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Add indirect clear color support to mcs_partial_resolveJason Ekstrand2018-03-011-1/+24
| | | | | | | | | | This is a bit complicated because we have to get the indirect clear color in there somehow. In order to not do any more work in the shader than needed, we set it up as it's own vertex binding which points directly at the clear color address specified by the client. Acked-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add a blorp_hiz_clear_depth_stencil helperJason Ekstrand2018-02-201-0/+53
| | | | | | | This is similar to blorp_gen8_hiz_clear_attachments except that it takes actual images instead of trusting in the already set depth state. Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Use isl_aux_op instead of blorp_hiz_opJason Ekstrand2018-02-081-1/+1
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Use isl_aux_op instead of blorp_fast_clear_opJason Ekstrand2018-02-081-5/+5
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Add a CCS ambiguation passJason Ekstrand2018-02-081-0/+153
| | | | | | | | | | | | This pass performs an "ambiguate" operation on a CCS-compressed surface by manually writing zeros into the CCS. On gen8+, ISL gives us a fairly detailed notion of how the CCS is laid out so this is fairly simple to do. On gen7, the CCS tiling is quite crazy but that isn't an issue because we can only do CCS on single-slice images so we can just blast over the entire CCS buffer if we want to. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Drop blorp_resolve_ccs_attachmentJason Ekstrand2017-11-271-50/+20
| | | | | | | | | | The only reason why we needed that version was because the Vulkan driver needed to be able to create the surface states so it could handle indirect clear colors. Now that blorp handles them natively, there's no need for the extra entrypoint. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/blorp: Take a range of layers in blorp_ccs_resolveJason Ekstrand2017-11-271-2/+5
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-311-9/+6
| | | | | | | | | The caller can now use brw_stage_prog_data::program_size which is set by the brw_compile_* functions. Cc: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Handle clearing compressed surfacesJason Ekstrand2017-09-201-7/+17
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/blorp: Support clearing L8_UNORM_SRGB surfacesJason Ekstrand2017-09-191-0/+4
| | | | | | | | Vulkan needs to be able to clear any texture you can create. We want to add support for VK_FORMAT_R8_SRGB and we need to use L8_UNORM_SRGB to do that so we need to be able to clear it. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: Add a partial resolve pass for MCSJason Ekstrand2017-07-221-1/+104
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* blorp/clear: Add a binding-table-based CCS resolve functionNanley Chery2017-06-261-17/+46
| | | | | | | | | | | | | v2: - Do layered resolves. (Jason Ekstrand): - Replace "bt" suffix with "attachment". - Rename helper function to prepare_ccs_resolve. - Move blorp_params_init() into helper function. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Check for layer fast-clear restrictionNanley Chery2017-06-261-0/+5
| | | | | | | | v2: Update commit title (Jason Ekstrand) Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Assert levels and layers are in rangeNanley Chery2017-06-261-4/+0
| | | | | | | | | | | | v2 (Jason Ekstrand): - Update commit title. - Check aux level and layer as well. v3 (Jason Ekstrand): - Move the non-aux layer check. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> (v1) Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Work around Sandy Bridge occlusion query issueJason Ekstrand2017-06-141-0/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Use BLORP for color clears on gen4-5Jason Ekstrand2017-05-261-0/+4
| | | | | | | | We don't support replicated data clears yet. Those take a bit more work and enabling replicated data clears in its own commit is probably better for bisectibility anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add blorp support for gen4-5Jason Ekstrand2017-05-261-5/+21
| | | | | | | | | | Due to complications with things such as URB setup on gen4-5, it's easier to keep gen4 support in blorp completely internal to i965. This makes things a bit awkward because that means there's a file in i965 that includes blorp_priv.h but it's either that or have a file in blorp that includes brw_context.h. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Add support for gen4-5 SF programsJason Ekstrand2017-05-261-0/+3
| | | | | | | | As part of enabling support for SF programs, we plumb the SF URB size through to emit_urb_config. For now, it's always zero but, on gen4, it may be something larger. Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e1af20f18a86f52a9640faf2d4ff8a71b0a4fa9b changed the shader_info from being embedded into being just a pointer. The idea was that sharing the shader_info between NIR and GLSL would be easier if it were a pointer pointing to the same shader_info struct. This, however, has caused a few problems: 1) There are many things which generate NIR without GLSL. This means we have to support both NIR shaders which come from GLSL and ones that don't and need to have an info elsewhere. 2) The solution to (1) raises all sorts of ownership issues which have to be resolved with ralloc_parent checks. 3) Ever since 00620782c92100d77c660f9783504c6d80fa1d58, we've been using nir_gather_info to fill out the final shader_info. Thanks to cloning and the above ownership issues, the nir_shader::info may not point back to the gl_shader anymore and so we have to do a copy of the shader_info from NIR back to GLSL anyway. All of these issues go away if we just embed the shader_info in the nir_shader. There's a little downside of having to copy it back after calling nir_gather_info but, as explained above, we have to do that anyway. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp: make upload_shader() return a bool indicating success or failureIago Toral Quiroga2017-03-161-18/+28
| | | | | | For now we always return true, follow-up patches will handle fail scenarios. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-1/+1
| | | | | | | | | | | | | | | | | | | Split out the EU defines from the 'generic' ones, as the former are more compiler oriented. With a later commit we'll move brw_eu_defines.h alongside the compiler infra to src/intel/. Pulling all the defines in there seems overzealous. Some defines are used by both i965 and the i965 compiler. Those are moved to brw_eu_defines.h, and annotated accordingly. The i965 users were updated to have the extre include to indicate that. With future work we might provide a better, split but for now this seems reasonable. Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Swizzle clear colors on the CPUJason Ekstrand2017-02-131-18/+30
| | | | | | | | | It's trivial to swizzle clear colors on the CPU, easily deals with the hardware restrictions for render target swizzles, and makes swizzled clears work on all hardware as opposed to just HSW+. Reviewed-by: Juan A. Suarez Romero <[email protected]> Cc: "17.0" <[email protected]>
* intel/blorp: Handle clearing of A4B4G4R4 on all platformsJason Ekstrand2017-01-311-0/+23
| | | | | | Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "13.0 17.0" <[email protected]>
* intel/blorp_clear: Add gen8 HiZ clearing functionsNanley Chery2017-01-121-0/+81
| | | | | | | | | | | | | Add an entry point for the optimized gen8 BLORP HiZ sequence. commit c9eaf12de20ac4143fe79d42018bdbb5a391356f fixed a bug that was unknowingly worked around by forcing additional clear rectangle alignment restrictions not specified in the PRMs. Now that the bug is no longer present, omit the additional alignment restrictions. v2: Adjust code comment about padding Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Fix rectangle size for level-not-zero resolvesTopi Pohjolainen2016-11-231-2/+2
| | | | | | | | Needed to prevent gpu hangs when mip-mapped compression gets enabled. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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