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* nir: Add addition/multiplication identities of exp/log.Matt Turner2015-04-011-0/+6
| | | | | | | instructions in affected programs: 2858 -> 2808 (-1.75%) helped: 12 Reviewed-by: Eric Anholt <[email protected]>
* nir: Add identities for the log function.Matt Turner2015-04-011-0/+8
| | | | | | | | | The rcp(log(x)) pattern affects instruction counts. instructions in affected programs: 144 -> 138 (-4.17%) helped: 6 Reviewed-by: Eric Anholt <[email protected]>
* nir: Add identities for the exponential function.Matt Turner2015-04-011-0/+6
| | | | | | No changes in shader-db. Reviewed-by: Eric Anholt <[email protected]>
* nir: Recognize another open coded lrp.Matt Turner2015-04-011-0/+1
| | | | | | | | | total instructions in shared programs: 6195924 -> 6195768 (-0.00%) instructions in affected programs: 4876 -> 4720 (-3.20%) helped: 58 HURT: 10 Reviewed-by: Eric Anholt <[email protected]>
* nir: Recognize open coded lrp.Matt Turner2015-04-011-0/+1
| | | | | | | | | total instructions in shared programs: 6197614 -> 6195924 (-0.03%) instructions in affected programs: 34773 -> 33083 (-4.86%) helped: 147 HURT: 6 Reviewed-by: Eric Anholt <[email protected]>
* nir/peephole_ffma: Be less agressive about fusing multiply-addsJason Ekstrand2015-04-011-0/+41
| | | | | | | | | | | | shader-db results for fragment shaders on Haswell: total instructions in shared programs: 4395688 -> 4389623 (-0.14%) instructions in affected programs: 355876 -> 349811 (-1.70%) helped: 1455 HURT: 14 GAINED: 5 LOST: 0 Reviewed-by: Matt Turner <[email protected]>
* nir: Add a dedicated ffma peephole optimizationJason Ekstrand2015-04-011-0/+220
| | | | | | | | | | | | | i965/nir: Use the dedicated ffma peephole total instructions in shared programs: 4418748 -> 4394618 (-0.55%) instructions in affected programs: 1292790 -> 1268660 (-1.87%) helped: 5999 HURT: 457 GAINED: 4 LOST: 9 Reviewed-by: Matt Turner <[email protected]>
* nir: Move the compare-with-zero optimizations to the late sectionJason Ekstrand2015-04-011-4/+4
| | | | | | | | | | | | | total instructions in shared programs: 4422307 -> 4422363 (0.00%) instructions in affected programs: 4230 -> 4286 (1.32%) helped: 0 HURT: 12 While this does hurt some things, the losses are minor and it prevents the compare-with-zero optimization from fighting with ffma which is much more important. Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Add a seperate section for "late" optimizationsJason Ekstrand2015-04-012-0/+10
| | | | | | i965/nir: Use the late optimizations Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: Remove a duplicate optimizationJason Ekstrand2015-04-011-3/+0
| | | | | | This optimization is repeated verbatim above Reviewed-by: Matt Turner <[email protected]>
* nir/algebraic: #define around structure definitionsJason Ekstrand2015-04-011-6/+11
| | | | | | | | Previously, we couldn't generate two algebraic passes in the same file because of multiple structure definitions. To solve this, we play the age-old header file trick and just #define around it. Reviewed-by: Matt Turner <[email protected]>
* nir/print: Don't print extra swizzzle componentsJason Ekstrand2015-04-011-7/+19
| | | | | | | | Previously, NIR would just print 4 swizzle components if the swizzle was anything other than foo.xyzw. This creates lots of noise if, for example, you have a one-component element with a swizzle of foo.xxxx. Reviewed-by: Kenneth Grunke <[email protected]>
* nir: Recognize a pattern of bool frobbing from TGSI KILL_IF.Eric Anholt2015-04-011-0/+2
| | | | | | | | | | | | TGSI's conditional discards take float arg and negate it, so GLSL to TGSI generates a b2f and negates that value. Only, in NIR we want a proper bool once again, so we compare with 0. This is a lot of pointless extra instructions. total instructions in shared programs: 39735 -> 39702 (-0.08%) instructions in affected programs: 1342 -> 1309 (-2.46%) Reviewed-by: Connor Abbott <[email protected]>
* nir: Recognize a pattern for doing b2f without the opcode.Eric Anholt2015-04-011-0/+1
| | | | | | | Since we have patterns based on b2f, generate them if we see the b2f equivalent using an iand. This is common when generating NIR from TGSI. Reviewed-by: Connor Abbott <[email protected]>
* nir: Fix copy and pasted error message in nir_validate.Kenneth Graunke2015-03-281-2/+1
| | | | | | | | | | These are nir_cf_nodes, not ALU instructions. Also, use unreachable() to preempt said review feedback. v2: Do it right (thanks Ilia). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Lower subtraction to add with negation when !lower_negate.Kenneth Graunke2015-03-271-0/+2
| | | | | | | | | | | prog->nir will generate fsub opcodes, but i965 doesn't implement them. We may as well lower them at the NIR level, since it's trivial to do. Suggested by Connor Abbott. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Add builder helpers for MOVs with ALU sources and swizzling MOVs.Kenneth Graunke2015-03-271-0/+44
| | | | | | | | | | These will be useful for prog->nir and tgsi->nir. v2: Don't forget to mark nir_swizzle as inline (Eric). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Add nir_builder helpers for creating load_const intrinsics.Kenneth Graunke2015-03-271-0/+35
| | | | | | | | Both prog->nir and tgsi->nir will want to use these. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Add optional lowering of flrp.Eric Anholt2015-03-272-0/+2
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir: Add glsl_float_type() wrapper.Kenneth Graunke2015-03-252-0/+7
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: Fix typo.Matt Turner2015-03-241-1/+1
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* nir: Recognize sat(add(b2f(a), b2f(b))) as a logical OR.Matt Turner2015-03-241-0/+1
| | | | | | | | | | | Transform this into b2f(or(a, b)). instructions in affected programs: 432 -> 430 (-0.46%) helped: 2 Acked-by: Ian Romanick <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Recognize mul(b2f(a), b2f(b)) as a logical AND.Matt Turner2015-03-241-0/+2
| | | | | | | | | | | | Transform this into b2f(and(a, b)). total instructions in shared programs: 6205448 -> 6204391 (-0.02%) instructions in affected programs: 284030 -> 282973 (-0.37%) helped: 903 HURT: 6 Acked-by: Ian Romanick <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir: Handle mixed scalar/vector arguments to logical and/or/xor.Matt Turner2015-03-241-18/+21
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_io: Add a assign_locations function that sorts by [in]direct useJason Ekstrand2015-03-192-0/+75
| | | | | | | v2: Delete the set of indirectly accessed variables when we're done with it v3: Rename from _packed to _scalar Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_io: Make variable location assignment a manual operationJason Ekstrand2015-03-192-12/+5
| | | | | | | | | | Previously, we just assigned variable locations in nir_lower_io. Now, we force the user to assign variable locations for us. This gives the backend a bit more control over where variables are placed. v2: Rename from _packed to _scalar Reviewed-by: Connor Abbott <[email protected]>
* nir: Use a list instead of a hash_table for inputs, outputs, and uniformsJason Ekstrand2015-03-196-35/+29
| | | | | | | | | | | | We never did a single hash table lookup in the entire NIR code base that I found so there was no real benifit to doing it that way. I suppose that for linking, we'll probably want to be able to lookup by name but we can leave building that hash table to the linker. In the mean time this was causing problems with GLSL IR -> NIR because GLSL IR doesn't guarantee us unique names of uniforms, etc. This was causing massive rendering isues in the unreal4 Sun Temple demo. Reviewed-by: Connor Abbott <[email protected]>
* mesa: Replace _mesa_round_to_even() with _mesa_roundeven().Matt Turner2015-03-182-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eric's initial patch adding constant expression evaluation for ir_unop_round_even used nearbyint. The open-coded _mesa_round_to_even implementation came about without much explanation after a reviewer asked whether nearbyint depended on the application not modifying the rounding mode. Of course (as Eric commented) we rely on the application not changing the rounding mode from its default (round-to-nearest) in many other places, including the IROUND function used by _mesa_round_to_even! Worse, IROUND() is implemented using the trunc(x + 0.5) trick which fails for x = nextafterf(0.5, 0.0). Still worse, _mesa_round_to_even unexpectedly returns an int. I suspect that could cause problems when rounding large integral values not representable as an int in ir_constant_expression.cpp's ir_unop_round_even evaluation. Its use of _mesa_round_to_even is clearly broken for doubles (as noted during review). The constant expression evaluation code for the packing built-in functions also mistakenly assumed that _mesa_round_to_even returned a float, as can be seen by the cast through a signed integer type to an unsigned (since negative float -> unsigned conversions are undefined). rint() and nearbyint() implement the round-half-to-even behavior we want when the rounding mode is set to the default round-to-nearest. The only difference between them is that nearbyint() raises the inexact exception. This patch implements _mesa_roundeven{f,}, a function similar to the roundeven function added by a yet unimplemented technical specification (ISO/IEC TS 18661-1:2014), with a small difference in behavior -- we don't bother raising the inexact exception, which I don't think we care about anyway. At least recent Intel CPUs can quickly change a subset of the bits in the x87 floating-point control register, but the exception mask bits are not included. rint() does not need to change these bits, but nearbyint() does (twice: save old, set new, and restore old) in order to raise the inexact exception, which would incur some penalty. Reviewed-by: Carl Worth <[email protected]>
* nir/peephole_select: Allow uniform/input loads and load_constJason Ekstrand2015-03-171-0/+25
| | | | | | | | | | | | | | | | | | | Shader-db results on HSW: total instructions in shared programs: 4174156 -> 4157291 (-0.40%) instructions in affected programs: 145397 -> 128532 (-11.60%) helped: 383 HURT: 0 GAINED: 20 LOST: 22 There are two more tests lost than gained. However, comparing this with GLSL IR vs. NIR results, the overall delta is reduced from 85/44 gained/lost on current master to 71/32 with this commit. Therefore, I think it's probably a boon since we are getting "closer" to where we were before. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Copy instructions into the block before the ifJason Ekstrand2015-03-171-13/+20
| | | | | | | | | Previously we tried to do poor-man's copy propagation as we created the select instructions. Instead, this commit just moves the instructions from the blocks inside the if into the block before. Copy propagation will take care of making sure we don't have any extra mov's in there for us. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Rename are_all_move_to_phi and use a switchJason Ekstrand2015-03-171-25/+31
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Fix non-determinism in nir_lower_vars_to_ssa().Kenneth Graunke2015-03-121-97/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we stored derefs in a hash table, using the malloc'd pointer as the key. Then, we walked through the hash table and generated code, based on the order of the hash table's elements. Memory addresses returned by malloc are pretty much random, which meant that the hash was random, and the hash table's elements would be walked in some random order. This led to successive compiles of the same shader using different variable names and slightly different orderings of phi-nodes. Code could not be diff'd, and the final assembly would sometimes change slightly too. It turns out the only point of the hash table was to avoid inserting the same node multiple times for different dereferences. We never actually searched the hash table! This patch uses an intrusive linked list instead. Since exec_list uses head and tail sentinels, checking prev or next against NULL will tell us whether the node is already in the list. Pair programming with Jason Ekstrand. Signed-off-by: Jason Ekstrand <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir: Add intrinsics for SYSTEM_VALUE_BASE_VERTEX and VERTEX_ID_ZERO_BASEKenneth Graunke2015-03-122-0/+8
| | | | | | | | | Ian and I added these around the time Connor was developing NIR. Now that both exist, we should make them work together! Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/worklist: Don't change the start index when computing the tail indexJason Ekstrand2015-03-112-7/+7
| | | | Reviewed-by: Mark Janes <[email protected]>
* nir: Optimize a + neg(a)Thomas Helland2015-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | Shader-db i965 instructions: total instructions in shared programs: 1711180 -> 1711159 (-0.00%) instructions in affected programs: 825 -> 804 (-2.55%) helped: 9 HURT: 0 GAINED: 3 LOST: 3 Shader-db NIR instructions: total instructions in shared programs: 606187 -> 606179 (-0.00%) instructions in affected programs: 298 -> 290 (-2.68%) helped: 4 HURT: 0 GAINED: 0 LOST: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Thomas Helland <[email protected]>
* nir: Optimize (a*b)+(a*c) -> a*(b+c)Thomas Helland2015-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | Shader-db i965 instructions: total instructions in shared programs: 1715894 -> 1710802 (-0.30%) instructions in affected programs: 443080 -> 437988 (-1.15%) helped: 1502 HURT: 13 GAINED: 4 LOST: 4 Shader-db NIR instructions: total instructions in shared programs: 607710 -> 606187 (-0.25%) instructions in affected programs: 208285 -> 206762 (-0.73%) helped: 769 HURT: 8 GAINED: 0 LOST: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Thomas Helland <[email protected]>
* nir: Make the printer include nir_variable::location too.Kenneth Graunke2015-03-091-1/+1
| | | | | | | | | Being able to see both location and driver_location can be useful when debugging IO mistakes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir: Only do gl_FrontFacing workaround in glsl_to_nir for the FS.Kenneth Graunke2015-03-081-1/+2
| | | | | | | | | | | | Vertex shaders can have shader inputs where location happens to be VARYING_SLOT_FACE. Without predicating this on the shader stage, we suddenly end up with load_front_face intrinsics in vertex shaders, which is nonsensical. Fixes spec/arb_vertex_buffer_object/pos-array when using NIR for VS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Plumb the shader stage into glsl_to_nir().Kenneth Graunke2015-03-082-7/+9
| | | | | | | | | The next commit needs to know the shader stage in glsl_to_nir(). To facilitate that, we pass the gl_shader rather than the raw exec_list of instructions. This has both the exec_list and the stage. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add native_integers to nir_shader_compiler_options.Kenneth Graunke2015-03-083-7/+12
| | | | | | | | | | | glsl_to_nir, tgsi_to_nir, and prog_to_nir all want to know whether the driver supports native integers. Presumably other passes may as well. Adding this to nir_shader_compiler_options is an easy way to provide that information, as it's accessible via nir_shader::options. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Try to make sense of the nir_shader_compiler_options code.Kenneth Graunke2015-03-082-28/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code in glsl_to_nir is entirely dead, as we translate from GLSL to NIR at link time, when there isn't a _mesa_glsl_parse_state to pass, so every caller passes NULL. glsl_to_nir seems like the wrong place to try and create the shader compiler options structure anyway - tgsi_to_nir, prog_to_nir, and other translators all would have to duplicate that code. The driver should set this up once with whatever settings it wants, and pass it in. Eric also added a NirOptions field to ctx->Const.ShaderCompilerOptions[] and left a comment saying: "The memory for the options is expected to be kept in a single static copy by the driver." This suggests the plan was to do exactly that. That pointer was not marked const, however, and the dead code used a mix of static structures and ralloced ones. This patch deletes the dead code in glsl_to_nir, instead making it take the shader compiler options as a mandatory argument. It creates an (empty) options struct in the i965 driver, and makes NirOptions point to that. It marks the pointer const so that we can actually do so without generating "discards const qualifier" compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: Delete nir_shader::user_structures and num_user_structures.Kenneth Graunke2015-03-084-22/+0
| | | | | | | | | | | Nothing actually uses these, and the only caller of glsl_to_nir() (brw_fs_nir.cpp) always passes NULL for the _mesa_glsl_parse_state pointer, meaning they'll always be NULL and 0, respectively. Just delete them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Use helper macros for dealing with VLAs.Jose Fonseca2015-03-044-24/+69
| | | | | | | | | | v2: - Single statement, by using memset return value as suggested by Ian Romanick. - No internal declaration, as suggested by Jason Ekstrand. - Move macros to a header. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Use alloca instead of variable length arrays.Jose Fonseca2015-02-273-16/+21
| | | | | | | | This is to enable the code to build with -Werror=vla in the short term, and enable the code to build with MSVC2013 soon after. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Introduce nir_intrinsic_discard_if.Kenneth Graunke2015-02-242-2/+10
| | | | | | | | | | | | This is a conditional discard, which takes a boolean source. Note that we don't generate ir_discard::condition today, so this shouldn't break drivers (since none implement this intrinsic yet). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/register: Add a parent_instr fieldJason Ekstrand2015-02-243-1/+18
| | | | | | | | | | | | | This adds a parent_instr field similar to the one for ssa_def. The difference here is that the parent_instr field on a nir_register can be NULL if the register does not have a unique definition or if that definition does not dominate all its uses. We set this field in the out-of-SSA pass so that backends can get SSA-like information even after they have gone out of SSA. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir/gcm: Add some missing break statementsJason Ekstrand2015-02-231-0/+4
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Copy-propagate vecN operations that are actually movesJason Ekstrand2015-02-231-16/+29
| | | | | | | | | | | | | | | | | | | We were already do this for ALU operations but we haven't for non-ALU operations. This changes that. total NIR instructions in shared programs: 2039883 -> 2022338 (-0.86%) NIR instructions in affected programs: 1768850 -> 1751305 (-0.99%) helped: 14244 HURT: 124 total FS instructions in shared programs: 4083960 -> 4084036 (0.00%) FS instructions in affected programs: 7302 -> 7378 (1.04%) helped: 12 HURT: 51 Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Generalize the optimization of subs of subs from 0.Eric Anholt2015-02-211-2/+2
| | | | | | | | | | | | I initially wrote this based on the "(('fneg', ('fneg', a)), a)" above, but we can generalize it and make it more potentially useful. In the specific original case of a 0 for our new 'a' argument, it'll get further algebraic optimization once the 0 is an argument to the new add. No shader-db effects. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* nir: Collapse repeated bcsels on the same argument.Eric Anholt2015-02-211-0/+1
| | | | | | | | | vc4 results: total instructions in shared programs: 39881 -> 39794 (-0.22%) instructions in affected programs: 6302 -> 6215 (-1.38%) Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
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