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* radeon/llvm: Cleanup AMDIL.hTom Stellard2012-07-304-91/+26
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* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-3030-496/+496
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* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-3025-324/+156
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* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-3011-241/+144
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* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-304-502/+2
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* radeon/llvm: Cleanup and reorganize AMDIL .td filesTom Stellard2012-07-3013-2303/+335
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* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-308-805/+50
| | | | e.g. function calls, load/store from stack
* radeon/llvm: Remove AMDILVersion.tdTom Stellard2012-07-302-59/+0
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* radeon/llvm: Remove AMDILAlgorithms.tppTom Stellard2012-07-302-94/+19
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* radeon/llvm: Merge AMDILInstrInfo.cpp into AMDGPUInstrInfo.cppTom Stellard2012-07-3012-693/+512
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* radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfoTom Stellard2012-07-3012-283/+69
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* radeon/llvm: Change the tablegen target from AMDIL to AMDGPUTom Stellard2012-07-3014-107/+119
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* radeonsi: fix db and stencil setup v2Christian König2012-07-303-67/+58
| | | | | | | | v2: fix tiling for small pitches, that finally makes glxgears and readPixSanity work Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix stencil op mappingChristian König2012-07-301-40/+34
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix assertion in si_bind_vs_samplerChristian König2012-07-301-1/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader bindingChristian König2012-07-301-2/+8
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix dummy export in shaders v2Christian König2012-07-301-0/+19
| | | | | | | v2: add assertion for vertex shader Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix vertex buffer and elementsChristian König2012-07-304-64/+74
| | | | | | | | Let's just use the T# descriptors until we get a fetch shader. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader size and handlingChristian König2012-07-301-13/+13
| | | | | | | | We should always upload the shader here. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: rename r600_resource to si_resourceChristian König2012-07-3015-94/+140
| | | | | | | | | Also split it into seperate header and add some helper functions. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* gallium: specify resource_resolve destination via a pipe_surfaceChristoph Bumiller2012-07-285-49/+33
| | | | | | | | | | | The format member of pipe_surface may differ from that of the pipe_resource, which is used to communicate, for instance, whether sRGB encode should be enabled in the resolve operation or not. Fixes resolve to sRGB surfaces in mesa/st when GL_FRAMEBUFFER_SRGB is disabled. Reviewed-by: Brian Paul <[email protected]>
* nv50: fix depth/stencil multisample memory storage typesChristoph Bumiller2012-07-281-6/+6
| | | | Leftover from libdrm_nouveau v2 interface change.
* nv50: fix resource_resolve shader start offsetsChristoph Bumiller2012-07-281-2/+2
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* r600g: Emit dispatch state for compute directly to the csTom Stellard2012-07-274-69/+60
| | | | | | | We no longer rely on an evergreen_compute_resource for emitting dispatch state. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Initialize VGT_PRIMITIVE_TYPE in the start_cs_cmd atomTom Stellard2012-07-271-2/+5
| | | | | | | The value of this register will always be DI_PT_POINTLIST for compute shaders. Reviewed-by: Marek Olšák <[email protected]>
* r600g: Atomize compute shader stateTom Stellard2012-07-274-86/+91
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: Add helper functions for emitting compute SET_CONTEXT packetsTom Stellard2012-07-272-5/+18
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add instruction defs for branches on SITom Stellard2012-07-273-17/+126
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* radeon/llvm: Fix VOPC and V_CNDMASK encodingTom Stellard2012-07-274-10/+13
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* radeon/llvm: Assert if we try to copy SCC regTom Stellard2012-07-271-0/+6
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* radeon/llvm: Add SI DAG optimizations for setcc, select_ccTom Stellard2012-07-272-0/+54
| | | | | These are needed for correctly lowering branch instructions in some cases.
* radeon/llvm: Add support for encoding SI branch instructionsTom Stellard2012-07-271-15/+35
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* radeon/llvm: Add special nodes for SALU operations on VCCTom Stellard2012-07-276-1/+89
| | | | | | | The VCC register is tricky because the SALU views it as 64-bit, but the VALU views it as 1-bit. In order to deal with this we've added some special bitcast and binary operations to help convert from the 64-bit SALU view to the 1-bit VALU view and vice versa.
* radeon/llvm: Add i1 registers for SI.Tom Stellard2012-07-271-0/+2
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* radeon/llvm: Fix CCReg definitions on SITom Stellard2012-07-272-3/+10
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* radeonsi: Enable PIPE_SHADER_CAP_INTEGERSTom Stellard2012-07-271-1/+2
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* radeonsi: Add support for loading integers from constant memoryTom Stellard2012-07-271-1/+3
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* radeon/llvm: Add bitconvert patterns for SITom Stellard2012-07-271-0/+6
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* radeon/llvm: Add custom lowering for SELECT_CC nodes on SITom Stellard2012-07-272-0/+20
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* radeon/llvm: Move conditional pattern leafs to common tablegen fileTom Stellard2012-07-272-41/+41
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* radeon/llvm: Implement getSetCCResultType for SITom Stellard2012-07-272-0/+6
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* radeon/llvm: Custom lower BR_CC for SITom Stellard2012-07-272-0/+41
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* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-274-31/+31
| | | | | SI will handle BR_CC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-274-38/+29
| | | | | SI will handle SETCC different from R600, so we need to move it out of the shared instruction selector.
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
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* radeon/llvm: Move LowerSELECT_CC into R600ISelLoweringTom Stellard2012-07-274-111/+112
| | | | | SI will handle SELECT_CC different from R600, so we need to move it out of the shared instruction selector.
* automake: Remove OPT_FLAGS.Eric Anholt2012-07-262-2/+0
| | | | | | | | | | If you want to change your compiler arguments, just set CFLAGS/CXXFLAGS. Having Mesa have this separate variable is a great way to have your arguments not thoroughly propagated to all compiler invocations. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Remove ARCH_FLAGS.Eric Anholt2012-07-262-2/+0
| | | | | | | | | | In all current uses, it was appended to CFLAGS, which already had -m32. If you want to do some other flag supplied to compiler invocations, there's CFLAGS/CXXFLAGS. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* svga: initialize svga_compile_key to zeros to be safeBrian Paul2012-07-261-0/+4
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* svga: fix invalid memory reference in needs_to_create_zero()Brian Paul2012-07-261-5/+5
| | | | | | | | | | | | | | The emit->key.fkey info is only valid if we're generating a fragment shader. We should not look at it if we're generating a vertex shader. When generating a vertex shader, the value of emit->key.fkey.num_textures was garbage and the loop over num_textures would read invalid data. At best this would cause us to emit an unused constant. At worse, we could segfault. Just by dumb luck, fkey.num_textures was usually a smallish integer. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: José Fonseca <[email protected]>
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