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* radeonsi: fix assertion and other failures in si_emit_graphics_shader_pointersMarek Olšák2020-01-141-3/+4
| | | | | | | The assertion was failing. Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* etnaviv: Fix assert when try to accumulate an invalid fdMarco Felsch2020-01-141-1/+2
| | | | | | | | | | Check if it is a valid fd before merging it to the context's fd. Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
* gallium: fix a warningErik Faye-Lund2020-01-141-1/+1
| | | | | | | | | | On some platforms (like Win64), unsigned long is 32-bit, so the first cast doesn't do anything, and the compiler complains about an implicit cast to a smaller type. So let's cast to an uintptr_t instead first, as that's large enough on all platforms. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/wgl: eliminate implicit cast warningErik Faye-Lund2020-01-141-2/+4
| | | | | | | | I get warnings on MSVC for these implicit casts. Let's use explicit casts instead. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* iris: Implement Gen12 workaround for non pipelined stateLionel Landwerlin2020-01-141-0/+39
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3365>
* lima: add new findings to texture descriptorVasily Khoruzhick2020-01-134-12/+47
| | | | | | | | | | | | | | | | | | | Lower 8 bits of unknown_1_3 seems to be min_lod, rest of 4 bits + miplevels are max_lod and min_mipfilter seems to be lod bias. All are in fixed format with 4 bit integer and 4 bit fraction, lod_bias also has sign bit. Blob also seems to do some magic with lod_bias if min filter is nearest -- it adds 0.5 to lod_bias in this case. Same story when all filters are nearest and mipmapping is enabled, but in this case it subtracts 1/16 from lod_bias. Fixes 134 dEQP tests in dEQP-GLES2.functional.texture.* Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3359>
* iris: Simplify iris_get_renderer_string()Kenneth Graunke2020-01-131-11/+4
| | | | | | | | | We use gen_get_device_name() instead of PCI ID list munging. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3371>
* zink: fixup initialization of operand_mask / num_extra_operandsErik Faye-Lund2020-01-141-2/+2
| | | | | | This doesn't change behavior, but makes the code a bit easier to read. Both values are zero, but I somehow swapped the logical meaning of them when initializing.
* radeonsi: don't enable VBOs in user SGPRs if compute-based culling can be usedMarek Olšák2020-01-133-30/+46
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: put up to 5 VBO descriptors into user SGPRsMarek Olšák2020-01-1310-62/+148
| | | | | | | | | | | | | | | | | | | | | gfx6-8: 1 VBO descriptor in user SGPRs gfx9-10: 5 VBO descriptors in user SGPRs We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled. Totals from affected shaders: SGPRS: 1110528 -> 1170528 (5.40 %) VGPRS: 952896 -> 951936 (-0.10 %) Spilled SGPRs: 83 -> 61 (-26.51 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 23766296 -> 22843920 (-3.88 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 179344 -> 179344 (0.00 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac,radeonsi: increase the maximum number of shader args and return valuesMarek Olšák2020-01-131-6/+6
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: simplify si_set_vertex_buffersMarek Olšák2020-01-131-7/+8
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: don't allow draw calls with uninitialized VS inputsMarek Olšák2020-01-133-1/+8
| | | | | | These always hang, because vertex buffer descriptors are not set up. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add si_context::num_vertex_elementsMarek Olšák2020-01-133-11/+7
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: rename desc_list_byte_size -> vb_desc_list_alloc_sizeMarek Olšák2020-01-135-11/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* nir/lower_atomics_to_ssbo: Also lower barriersJason Ekstrand2020-01-131-2/+0
| | | | | | | | | | | This is more correct for a pass which is supposed to completely lower away atomic counters. It also lets us stop supporting atomic counter barriers in most of the drivers. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Rename nir_intrinsic_barrier to control_barrierJason Ekstrand2020-01-132-2/+2
| | | | | | | | This is a more explicit name now that we don't want it to be doing any memory barrier stuff for us. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* nir: Add a new memory_barrier_tcs_patch intrinsicJason Ekstrand2020-01-132-0/+3
| | | | | | | | | | | Right now, it's implemented as a no-op for everyone. For most drivers, it's a switch case in the NIR -> whatever which just breaks. For ir3, they already have code to delete tessellation barriers so we just add a case to also delete memory_barrier_tcs_patch. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* llmvpipe: No-op implement more barriersJason Ekstrand2020-01-131-0/+3
| | | | | Acked-by: Dave Airlie <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3307>
* lima: Add stencil supportAndreas Baierl2020-01-132-27/+64
| | | | | | | | | | | | | | This re-enables and fixes support for stencil buffer. It fixes 365 stencil related deqp tests. All tests that use INCR, INCR_WRAR, DECR and DECR_WRAP as a stencil op still fail, but they also fail with the blob, so we may ignore that for now. We still have dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked failing, which is strange because it's the only one out of the depth_stencil_clear.* set. Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* lima/parser: Make rsw alpha blend parsing more readableAndreas Baierl2020-01-131-4/+5
| | | | | Reviewed-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Andreas Baierl <[email protected]>
* panfrost: Fix headers and gpu_headers memory leakDaniel Ogorchock2020-01-131-0/+3
| | | | | | | | | | The per-batch headers/gpu_headers dynarrays need to be freed during the batch cleanup to prevent leaking. Signed-off-by: Daniel Ogorchock <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
* panfrost: Fix panfrost_bo_access memory leakDaniel Ogorchock2020-01-131-1/+3
| | | | | | | | | The bo access needs to be freed prior to removing it from its hash table. This prevents leaking them over time. Signed-off-by: Daniel Ogorchock <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3308>
* nvc0: treat all draws without color0 broadcast as MRTIlia Mirkin2020-01-121-1/+1
| | | | | | | | | | | Per the semi-recently-released NVIDIA docs, when this bit is not enabled, then the result for RT[0] will be used. So if e.g. only a single RT is drawn to and it's not RT[2], the results will not be visible. Fixes GTF-GL45.gtf33.GL3Tests.explicit_attrib_location.explicit_attrib_location_pipeline which was failing due to a frag shader outputting only to location=2. Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: avoid combining geometry shader stores at 0x60Ilia Mirkin2020-01-121-0/+10
| | | | | | | | | | | | This corresponds to gl_PrimitiveID and gl_Layer. When both of these are stored in a single AST.64 or AST.128 operation, then it appears as though the whole store fails. Fixes the recently extended glsl-1.50-transform-feedback-builtins piglit, and also gtf30.GL3Tests.transform_feedback.transform_feedback_builtins. The issue was reproduced on GM107 and GP108 but not GK208 nor GK104. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add dummy reset status supportIlia Mirkin2020-01-122-1/+8
| | | | | | | | Perhaps in a future implementation, such events could be passed back to the driver, or queried directly. However for now, this is required for GL 4.3 robustness contexts. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50,nvc0: fix destination coordinates of blitIlia Mirkin2020-01-122-10/+18
| | | | | | | | | | | | | | | | | | | | | | | The fix was found by Karol Herbst a long time ago, but it was unclear why it helped or if it would create additional problems. This change adds a comment that explains what's going on, and in the process also normalizes the nv50 implementation to match. The coordinates which are fed to gl_Position map directly to pixel coordinates, since the viewport transform is disabled. If the framebuffer is MSAA, then that doesn't affect the pixel coordinates at all, it's just that each pixel has multiple samples. Note that this makes it really clear that this approach is inappropriate for EXT_framebuffer_multisample_blit_scaled, and also the 3d path will fail terribly for direct copies. Thankfully the 2d path normally takes care of this. Fixes KHR-GL43.packed_depth_stencil.blit.depth32f_stencil8 as well as scaling issues in a number of EXT_framebuffer_multisample-related piglit tests (although they continue to fail due to inaccuracies). Signed-off-by: Ilia Mirkin <[email protected]>
* lima: fix PIPE_CAP_* to mark features that aren't supported yetVasily Khoruzhick2020-01-121-0/+6
| | | | | | | | | | lima doesn't support alpha test, flat shading, two-sided color nor clip planes. We can enable these caps when corresponding hw features are implemented in the driver. Reviewed-by: Qiang Yu <[email protected]> Tested-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: implement polygon offsetVasily Khoruzhick2020-01-121-14/+9
| | | | | | | | Fixes some of dEQP-GLES2.functional.polygon_offset.* tests and shadows in Q3A. Reviewed-by: Qiang Yu <[email protected]> Tested-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: fix viewport clippingVasily Khoruzhick2020-01-121-5/+17
| | | | | | | | | | | | | | | Apparently Mali4x0 doesn't do viewport clipping, so anything rendered beyond viewport is still rendered. Looks like we need to use scissors to do clipping. Fixes most of dEQP-GLES2.functional.clipping.*, 6 out of 7 remaining failures fail on blob as well. Remaining [1] fails on many other gallium drivers. [1] dEQP-GLES2.functional.clipping.triangle_vertex.clip_three.clip_neg_x_neg_z_and_pos_x_pos_z_and_neg_x_neg_y_pos_z Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Qiang Yu <[email protected]> Tested-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: fix PLBU_CMD_PRIMITIVE_SETUP commandVasily Khoruzhick2020-01-122-21/+16
| | | | | | | | | | Apparently it doesn't depend on primitive type, the value only depends on whether we specify point size via PLBU command -- bit 12 is set in this case Reviewed-by: Qiang Yu <[email protected]> Tested-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* etnaviv: add deqp debug optionChristian Gmeiner2020-01-112-1/+8
| | | | | | | | | | This new debug option will fake some driver CAPs to be able to run dEQP for GLES3. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3351>
* radeonsi: release saved resources in si_compute_do_clear_or_copyPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 9b331e462e5 ("radeonsi: use compute shaders for clear_buffer & copy_buffer") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_clear_12bytes_bufferPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 6c901f06752 ("radeonsi: use compute shader for clear 12-byte buffer") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_copy_imagePierre-Eric Pelloux-Prayer2020-01-101-0/+3
| | | | | Fixes: 1b25d340b79 ("radeonsi: use compute for resource_copy_region when possible") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_clear_render_targetPierre-Eric Pelloux-Prayer2020-01-101-0/+2
| | | | | Fixes: 984fd735152 ("radeonsi: use compute for clear_render_target when possible") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_compute_expand_fmaskPierre-Eric Pelloux-Prayer2020-01-101-0/+1
| | | | | Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used") Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release saved resources in si_retile_dccPierre-Eric Pelloux-Prayer2020-01-101-0/+4
| | | | | | Fixes: 1f21396431a ("radeonsi: add support for displayable DCC for multi-RB chips") Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2330 Reviewed-by: Marek Olšák <[email protected]>
* panfrost: Add negative lod bias supportIcecream952020-01-101-3/+3
| | | | Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl/drm: update UAPIGurchetan Singh2020-01-102-175/+1
| | | | | | | This seems to compile. Header copied over from drm-misc-next 7da5492739db. Acked-by: Eric Engestrom <[email protected]>
* lima: drop support for R8G8B8 formatVasily Khoruzhick2020-01-091-1/+0
| | | | | | | | | We can only sample from 24-bit packed format and can't render into it and it causes chromium-based browsers to fail when they create FBO with GL_RGB format. Drop R8G8B8 alltogether so mesa can promote it to RGBX format. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: add debug flag to disable tilingVasily Khoruzhick2020-01-103-1/+4
| | | | | | | | | Add debug flag to disable tiling. Note that it prevents lima from creating tiled buffers, but it's still able to import them if modifier is specified Reviewed-by: Andreas Baierl <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: use linear layout for shared buffers if modifier is not specifiedVasily Khoruzhick2020-01-101-1/+8
| | | | | | | | | | Use linear layout for shared buffers if modifier is not specified and use linear layout when importing buffers with invalid modifier. Fixes: 01a451b04d2d ("lima: handle DRM_FORMAT_MOD_INVALID in resource_from_handle()") Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* llvmpipe: add ARB_derivative_control supportDave Airlie2020-01-102-1/+5
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9Marek Olšák2020-01-093-1/+15
| | | | | | | Fixes: 69ea473 "amd/addrlib: update to the latest version" Closes: #2325 Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeon/vcn: Handle crop parameters for encoderSatyajit Sahu2020-01-091-4/+11
| | | | | | | | | Set proper cropping parameter if frame cropping is enabled Signed-off-by: Satyajit Sahu <[email protected]> Reviewed-by: Boyuan Zhang [email protected] Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3328>
* spirv,nir: add new lod parameter to image_{load,store} intrinsicsSamuel Pitoiset2020-01-091-0/+5
| | | | | | | | | | | | SPV_AMD_shader_image_load_store_lod allows to use a lod parameter with OpImageRead, OpImageWrite and OpImageSparseRead. According to the specification, this parameter should be a 32-bit integer. It is initialized to 0 when no lod parameter is found during SPIR-V->NIR translation. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* llvmpipe: add support for ARB_indirect_parameters.Dave Airlie2020-01-092-2/+19
| | | | | | | | | This just adds support for getting the draw count from the indirect buffer. Reviewed-by: Roland Scheidegger <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
* llvmpipe: enable driver side multi draw indirectDave Airlie2020-01-091-1/+2
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
* gallium/util: add multi_draw_indirect to util_draw_indirect.Dave Airlie2020-01-091-9/+13
| | | | | | | | ARB_indirect_parameters needs drivers to deal with mutli_draw_indirect themselves. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3234>
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