| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | gallium: Add context hooks for binding shader resources. | Francisco Jerez | 2012-05-11 | 5 | -1/+58 | |
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| * | | gallium/tgsi: Split sampler views from shader resources. | Francisco Jerez | 2012-05-11 | 17 | -183/+303 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit splits the current concept of resource into "sampler views" and "shader resources": "Sampler views" are textures or buffers that are bound to a given shader stage and can be read from in conjunction with a sampler object. They are analogous to OpenGL texture objects or Direct3D SRVs. "Shader resources" are textures or buffers that can be read and written from a shader. There's no support for floating point coordinates, address wrap modes or filtering, and, unlike sampler views, shader resources are global for the whole graphics pipeline. They are analogous to OpenGL image objects (as in ARB_shader_image_load_store) or Direct3D UAVs. Most hardware is likely to implement shader resources and sampler views as separate objects, so, having the distinction at the API level simplifies things slightly for the driver. This patch introduces the SVIEW register file with a declaration token and syntax analogous to the already existing RES register file. After this change, the SAMPLE_* opcodes no longer accept a resource as input, but rather a SVIEW object. To preserve the functionality of reading from a sampler view with integer coordinates, the SAMPLE_I(_MS) opcodes are introduced which are similar to LOAD(_MS) but take a SVIEW register instead of a RES register as argument. | |||||
| * | | gallium: Basic compute interface. | Francisco Jerez | 2012-05-11 | 7 | -2/+185 | |
| | | | | | | | | | | | | | | | | | | | | | Define an interface that exposes the minimal functionality required to implement some of the popular compute APIs. This commit adds entry points to set the grid layout and other state required to keep track of the usual address spaces employed in compute APIs, to bind a compute program, and execute it on the device. Reviewed-by: Marek Olšák <[email protected]> | |||||
| * | | radeonsi: Properly translate vertex format swizzle. | Michel Dänzer | 2012-05-11 | 3 | -23/+23 | |
| | | | | | | | | | egltri_screen works correctly! | |||||
| * | | radeon/llvm: Remove AMDILMCCodeEmitter.cpp | Tom Stellard | 2012-05-10 | 2 | -158/+0 | |
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| * | | radeon/llvm: Remove SILowerShaderInstructions.cpp | Tom Stellard | 2012-05-10 | 4 | -81/+0 | |
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| * | | radeonsi/llvm: Move lowering of RETURN to ConvertToISA pass | Tom Stellard | 2012-05-10 | 2 | -11/+2 | |
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| * | | radeon/llvm: Add some comments | Tom Stellard | 2012-05-10 | 64 | -422/+393 | |
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| * | | radeon/llvm: Move util functions into AMDGPU namespace | Tom Stellard | 2012-05-10 | 3 | -39/+37 | |
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| * | | radeon/llvm: Auto-encode RAT_WRITE_CACHELESS_eg | Tom Stellard | 2012-05-10 | 2 | -17/+0 | |
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| * | | radeon/llvm: Delete all instructions that have been custom lowered | Tom Stellard | 2012-05-10 | 1 | -4/+1 | |
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| * | | radeonsi: Set NONE format for unused vertex shader position export slots. | Michel Dänzer | 2012-05-10 | 1 | -3/+3 | |
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| * | | radeonsi: Eliminate one more magic number for texture image resources. | Michel Dänzer | 2012-05-10 | 1 | -3/+3 | |
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| * | | radeonsi: Fix vertex buffer resource for stride 0. | Michel Dänzer | 2012-05-10 | 1 | -1/+5 | |
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| * | | radeon/llvm: Remove AMDGPUConstants.pm | Tom Stellard | 2012-05-09 | 2 | -45/+23 | |
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| * | | radeon/llvm: Don't rely on tablegen for lowering int_AMDGPU_load_const | Tom Stellard | 2012-05-09 | 5 | -38/+20 | |
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| * | | radeon/llvm: Make sure the LOAD_CONST def uses the isSI predicate | Tom Stellard | 2012-05-09 | 2 | -7/+7 | |
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| * | | svga: implement CEIL opcode translation | Brian Paul | 2012-05-09 | 1 | -0/+28 | |
| | | | | | | | | | Reviewed-by: José Fonseca <[email protected]> | |||||
| * | | gallium/drivers: handle TGSI_OPCODE_CEIL | Christoph Bumiller | 2012-05-09 | 4 | -0/+28 | |
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| * | | r600g: Handle TGSI_OPCODE_CEIL (v2) | Kai Wasserbäch | 2012-05-09 | 1 | -3/+3 | |
| | | | | | | | | | | | | | | | v2: Enabled CEIL on Cayman too. Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Tom Stellard <[email protected]> | |||||
| * | | gallivm: implement iabs/issg opcode. | Dave Airlie | 2012-05-09 | 2 | -1/+26 | |
| | | | | | | | | | | | | | Reimplemented by Olivier Galibert <[email protected]> Signed-off-by: Dave Airlie <[email protected]> | |||||
| * | | radeon/llvm: Remove AMDILUtilityFunctions.cpp | Tom Stellard | 2012-05-08 | 13 | -1041/+399 | |
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| * | | radeon/llvm: Remove some unused functions from AMDILInstrInfo | Tom Stellard | 2012-05-08 | 2 | -164/+0 | |
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| * | | radeon/llvm: Add some comments and fix coding style | Tom Stellard | 2012-05-08 | 8 | -42/+41 | |
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| * | | radeon/llvm: Remove the EXPORT_REG instruction | Tom Stellard | 2012-05-08 | 10 | -117/+8 | |
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| * | | radeon/llvm: Use a custom inserter to lower RESERVE_REG | Tom Stellard | 2012-05-08 | 10 | -27/+83 | |
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| * | | radeon/llvm: Use a custom inserter to lower STORE_OUTPUT | Tom Stellard | 2012-05-08 | 4 | -34/+23 | |
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| * | | radeon/llvm: Remove AMDGPULowerShaderInstructions class | Tom Stellard | 2012-05-08 | 6 | -86/+4 | |
| | | | | | | | | | It is no longer used. | |||||
| * | | radeon/llvm: Use a custom inserter to lower LOAD_INPUT | Tom Stellard | 2012-05-08 | 4 | -39/+15 | |
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| * | | radeon/llvm: Remove the ReorderPreloadInstructions pass | Tom Stellard | 2012-05-08 | 9 | -100/+4 | |
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| * | | radeon/llvm: Remove old comment from AMDIL.h | Tom Stellard | 2012-05-08 | 1 | -5/+0 | |
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| * | | radeon/llvm: add suport for cube textures | Vadim Girlin | 2012-05-08 | 2 | -23/+91 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for CUBE ALU instruction | Vadim Girlin | 2012-05-08 | 5 | -21/+63 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for some ALU instructions | Vadim Girlin | 2012-05-08 | 4 | -13/+293 | |
| | | | | | | | | | | | | | | | | | Add support for IABS, NOT, AND, XOR, OR, UADD, UDIV, IDIV, MOD, UMOD, INEG, I2F, U2F, F2U, F2I, USEQ, USGE, USLT, USNE, ISGE, ISLT, ROUND, MIN, MAX, IMIN, IMAX, UMIN, UMAX Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add missing cases for BREAK/CONTINUE | Vadim Girlin | 2012-05-08 | 2 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for AHSR/LSHR/LSHL instructions | Vadim Girlin | 2012-05-08 | 4 | -0/+53 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for TXQ/TXF/DDX/DDY instructions | Vadim Girlin | 2012-05-08 | 6 | -6/+43 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for VertexID, InstanceID | Vadim Girlin | 2012-05-08 | 3 | -0/+50 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: fix live-in handling for inputs | Vadim Girlin | 2012-05-08 | 2 | -2/+3 | |
| | | | | | | | | | | | | | Set the input registers as live-in for entry basic block. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: add support for v4i32 | Vadim Girlin | 2012-05-08 | 4 | -5/+20 | |
| | | | | | | | | | Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: fix ABS_i32 instruction lowering | Vadim Girlin | 2012-05-08 | 1 | -2/+2 | |
| | | | | | | | | | | | | | Swap source operands. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: use integer comparison for IF | Vadim Girlin | 2012-05-08 | 1 | -2/+4 | |
| | | | | | | | | | | | | | | | Replacing "float equal to 1.0f" with "int not equal to 0". This should help for further optimization of boolean computations. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | radeon/llvm: use bitcasts for integers | Vadim Girlin | 2012-05-08 | 3 | -5/+73 | |
| | | | | | | | | | | | | | | | | | | | We're using float as default type, so basically for every instruction that wants other types for dst/src operands we need to perform the bitcast to/from default float. Currently bitcast produces no-op MOV instruction, will be eliminated later. Signed-off-by: Vadim Girlin <[email protected]> | |||||
| * | | r600g: Fix out of tree builds that use the LLVM backend | Tom Stellard | 2012-05-07 | 1 | -1/+1 | |
| | | | | | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=49567 | |||||
| * | | radeon/llvm: Remove references to DebugFlag and isCurrentDebugType() | Tom Stellard | 2012-05-07 | 4 | -22/+3 | |
| | | | | | | | | | | | | | | | These weren't being used at all and they were causing build failures when LLVM was built with NDEBUG defined and mesa was not. https://bugs.freedesktop.org/show_bug.cgi?id=49110 | |||||
| * | | nv50: handle VP without inputs | Marcin Slusarz | 2012-05-07 | 1 | -0/+11 | |
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| * | | nvc0/ir: allow abs,neg source modifiers with ceil,floor,trunc | Christoph Bumiller | 2012-05-06 | 1 | -0/+3 | |
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| * | | nv50/ir/opt: don't lose saturation in tryCollapseChainedMULs | Christoph Bumiller | 2012-05-06 | 1 | -2/+3 | |
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| * | | nvc0/ir: fix lowering of textureGrad | Christoph Bumiller | 2012-05-06 | 3 | -12/+13 | |
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| * | | nouveau: fix nouveau_scratch_runout_release bo count underflow | Christoph Bumiller | 2012-05-06 | 1 | -1/+3 | |
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