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* meson: don't use build_by_default for specific gallium driversDylan Baker2017-11-1313-34/+25
| | | | | | | | | | | | | | | | | | | Using build_by_default : false is convenient for dependencies that can be pulled in by various diverse components of the build system, the gallium hardware/software drivers and state trackers do not fit that description. Instead, these should be guarded using the variable that tracks whether that driver should be enabled. This leaves a few helper libraries: trace, rbug, etc, and the generic winsys bits as `build_by_default : false` because there are a large number of gallium components that pull them in. v2: - remove build_by_default from winsys convenience libs as well. v3: - Always put drivers before winsys for consistency Signed-off-by: Dylan Baker <[email protected]> Tested-by: Lionel Landwerlin <[email protected]> (v1) Reviewed-by: Eric Anholt <[email protected]>
* r600/shader: handle bitfield extract semantics properly.Dave Airlie2017-11-141-4/+53
| | | | | | | Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldExtract.shader_test Signed-off-by: Dave Airlie <[email protected]>
* r600: handle bitfieldInsert corner case.Dave Airlie2017-11-141-1/+39
| | | | | | | | | This handles the bits >= 32 corner case in bitfieldInsert. Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldInsert.shader_test. Signed-off-by: Dave Airlie <[email protected]>
* r600: add gs tri strip adjacency fix.Dave Airlie2017-11-144-5/+62
| | | | | | | | | | | | | | Like radeonsi: generate GS prolog to (partially) fix triangle strip adjacency rotation evergreen hw suffers from the same problem, so rotate the geometry inputs to fix this. This fixes: ./bin/glsl-1.50-geometry-primitive-types GL_TRIANGLE_STRIP_ADJACENCY on evergreen. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix isoline tess factor component swapping.Dave Airlie2017-11-141-0/+7
| | | | | | | | | As per radeonsi, the tess factor components for isolines are reversed. Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: reserve first register of vertex shader.Dave Airlie2017-11-141-2/+4
| | | | | | | | | | r0 in input into vertex shaders contains things like vertexid, we need to reserve it even if we have no inputs. This fixes a bunch of tessellation piglits. Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: don't emit atomic save if we have no atomic counters.Dave Airlie2017-11-141-0/+3
| | | | | | | Otherwise we end up emitting the fence. Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* etnaviv: automake,meson: include common_3d.xml.h in the sources listsJuan A. Suarez Romero2017-11-132-0/+2
| | | | | | | v2: include the file also in the meson.build (Eric Engestrom). Fixes: f1e1c60ff6 ("etnaviv: Update from rnndb") Reviewed-by: Eric Engestrom <[email protected]>
* freedreno/a5xx: fix SSBO emit for non-zero offsetRob Clark2017-11-121-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove obsolete commentRob Clark2017-11-121-4/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't create split/fo if only writing .xRob Clark2017-11-121-0/+6
| | | | | | | In case an instruction only writes one register, and it is .x, we can skip the extra level of fanout indirection. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: indirect gridsRob Clark2017-11-123-20/+86
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add global size compute capRob Clark2017-11-121-0/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: turn on std430 packingRob Clark2017-11-121-1/+6
| | | | | | Seems to fix dEQP compute related tests.. and matches what i965 does, so perhaps there is some assumption that std430 packing is on by default somewhere in NIR?
* freedreno/a5xx: image supportRob Clark2017-11-128-31/+306
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* freedreno/ir3: moar better schedulerRob Clark2017-11-125-58/+227
| | | | | | | | | | | | | | | | | | Add a new pass that inserts additional dependencies, rather than simply relying on SSA srcs added in the nir->ir3 frontend. This makes it easier to deal with barriers, but the additional false deps also lets us deal properly with ensuring a write depends on all previous reads. Since conversion to barrier instructions is lossy (ie. just knowing the instruction doesn't tell us enough about what other instructions the barrier applies to), use barrier_class/barrier_conflict fields in the ir3_instruction to retain this information. This could probably be relaxed somewhat by considering *which* array/ buffer/image variable is being referenced. Ie. a write to buffer A can overtake a read from buffer B, if B is not coherent. (right?) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move macrosRob Clark2017-11-121-15/+15
| | | | | | | | | | I want to add a growable array to ir3_instruction, so we can append false dependencies for purposes of scheduling barriers, atomics, and dealing with write after read hazards. Just code motion preparing for next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image supportRob Clark2017-11-125-0/+337
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: shared variable supportRob Clark2017-11-123-2/+177
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: some SSBO cleanups/fixesRob Clark2017-11-122-15/+39
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out INSTR4F instructionsRob Clark2017-11-122-29/+64
| | | | | | | | Atomic instructions take a different # of src args depending on .g or .l variant, split these out into different helpers with INSTR*F() helper macro that lets you specify instruction flag. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cat6 encoding fixesRob Clark2017-11-124-32/+151
| | | | | | | Instruction encoding/decoding fixes needed for images, shared variables, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add barriersRob Clark2017-11-122-0/+55
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: invert is_same_type_mov() logicRob Clark2017-11-121-10/+16
| | | | | | | | Some instructions (like barriers) have no dst, which causes problems with dereferencing a NULL dst. Flip the logic around to reject opc's that can't be a type of move first, to filter out those instructions. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add cat7 instructionsRob Clark2017-11-124-2/+79
| | | | | | Needed for memory and execution barriers. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add SSBO get_buffer_size() supportRob Clark2017-11-126-11/+122
| | | | | | Somehow I overlooked this when adding initial SSBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: extract helper for common constsRob Clark2017-11-121-34/+17
| | | | | | | | User consts and driver consts such as UBO addresses and immediates are handled the same for all shader stages, so split out a shared helper for these, to make it easier to add more. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add image view state trackingRob Clark2017-11-122-0/+56
| | | | | | | | | It is unfortunate that image state isn't a real CSO, since (at least for a4xx/a5xx) it is a combination of sampler and "SSBO" image state, and it would be useful to pre-compute the state block "register" values rather than doing it at emit time. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-11-126-19/+142
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename ir3_compile -> ir3_contextRob Clark2017-11-121-57/+57
| | | | | | | | | Having both an ir3_compile (which was really context for compiling a single shader variant) and ir3_compiler (which is the compiler object that compiles all variants, ie. basically holds the RA regset) is a bit confusing. Signed-off-by: Rob Clark <[email protected]>
* ac: add emit_vertex to the abiTimothy Arceri2017-11-121-14/+21
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rework gs_vtx_offset handlingTimothy Arceri2017-11-122-22/+10
| | | | | | | This simplifies things a bit and will enable it to work with the common NIR -> LLVM code. Reviewed-by: Marek Olšák <[email protected]>
* st/dri: fix deadlock when waiting on android fencesMarek Olšák2017-11-112-4/+2
| | | | | | | Android fences can't be deferred, because st/dri calls fence_finish with ctx = NULL, so the driver can't flush u_threaded_context. Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: Guard freedreno build with with_gallium_freedreno.Rob Clark2017-11-101-1/+3
| | | | | | | | | | This prevents build failures when libdrm_freedreno is unavailable, which started happening after the ir3_compiler build was enabled. (Patch by Rob, commit message by Ken). Fixes: fecd04a66ae ("freedreno/ir3: fix standalone compiler meson build") Reviewed-by: Kenneth Graunke <[email protected]>
* meson: build gallium-xlib based glxDylan Baker2017-11-104-2/+131
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: add nir_builder_opcodes_h to gallium_auxiliaryDylan Baker2017-11-101-1/+1
| | | | | | | | | This creates a dependency on this header being generated before trying to compile any of these targets, as well as passing the correct -I to the compiler to ensure it's included correctly. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/xlib: remove GL_{MAJOR,MINOR,TINY}Dylan Baker2017-11-101-5/+1
| | | | | | | | | | | | | These variables were removed from autotools in 2008 (sha: 80f68e1b6a0e5bd2da799c), but they have lived on here. The Scons build meanwhile doesn't set a patch/tiny version at all, just major and minor. This patch removes the unused variables and simply sets the version, leaving patch/tiny as 0 since that's what the autotools build as been doing forever. This shouldn't change any behavior. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi: get llvm types from acTimothy Arceri2017-11-111-4/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/dri: fix android fence regressionMarek Olšák2017-11-102-1/+3
| | | | | | | | | | | | | Fixes piglit - egl_khr_fence_sync/android_native tests. Broken by 884a0b2a9e55d4c1ca39475b50d9af598d7d7280. Introduce state-tracker flush flags, analogous to the pipe ones. Use the former when with stapi->flush(). Fixes: 884a0b2a9e5 ("st/dri: use stapi flush instead of pipe flush when creating fences") Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: fix end_query regressionNicolai Hähnle2017-11-101-2/+0
| | | | | | | | Ouch... Fixes: 244536d3d6b4 ("gallium/u_threaded: avoid syncs for get_query_result") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103653 Reviewed-by: Marek Olšák <[email protected]>
* swr: Fixed an uncommon freed-memory access during state validationBruce Cherniak2017-11-102-17/+25
| | | | | | | | | | | | | | | | | | | | | State validation is performed during clear and draw calls. Validation during clear was still accessing vertex buffer state. When the currently set vertex buffers are client arrays, this could lead to accessing freed memory. Such is the case with the VMD application. Previously, vertex buffer validation depended on a dirty bit or the draw info indicating an indexed draw. This required special handling for clears. But, vertex buffer validation still occurred which was unnecessary and wrong. Now, only minimal validation is performed during clear, deferring the remainder to the next draw. And, by setting the dirty bit in swr_draw_vbo for indexed draws, vertex buffer validation is only dependent upon a single dirty bit. This fixes a bug exposed by the VMD application when changing models. Reviewed-By: George Kyriazis <[email protected]>
* freedreno/ir3: fix standalone compiler meson buildRob Clark2017-11-101-3/+13
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: correct # of dest components for intrinsicsRob Clark2017-11-101-1/+6
| | | | | | | Don't rely on intr->num_components having a valid value. It doesn't seem to anymore for non-vectorized intrinsics. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove bogus assertRob Clark2017-11-101-1/+0
| | | | | | | The ssbo atomic instructions are not vectorized. So num_components is not expected to be valid. Signed-off-by: Rob Clark <[email protected]>
* broadcom/vc4: Fix simulator mode for the MADVISE usage.Eric Anholt2017-11-091-0/+4
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* r600: add support for hw atomic counters. (v3)Dave Airlie2017-11-107-22/+480
| | | | | | | | | | | | | | | | This adds support for the evergreen/cayman atomic counters. These are implemented using GDS append/consume counters. The values for each counter are loaded before drawing and saved after each draw using special CP packets. v2: move hw atomic assignment into driver. v3: fix messing up caps (Gert Wollny), only store ranges in driver, drop buffers. Signed-off-by: Dave Airlie <[email protected]> Acked-by: Nicolai Hähnle <[email protected]> Tested-By: Gert Wollny <[email protected]>
* gallium: add hw atomic buffer binding API.Dave Airlie2017-11-102-0/+24
| | | | | | | | | | | | This API binds atomic buffers for all bound shaders (as per the GL semantics). This is needed to support cross shader hw atomic counters. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/tgsi: start adding hw atomics (v3.2)Dave Airlie2017-11-106-3/+121
| | | | | | | | | | | | | | | | | | | | | This adds support for a hw atomic counters to TGSI. A new register file for storing atomic counters is added, along with a new atomic counter semantic, along with docs for both. v2: drop semantic, move hw counter to backend, Ilia pointed out SSO would have busted my plan, and he was right. v3: drop BUFFER decls. (Marek) v3.1: minor fixups for whitespace, set ureg error if we overflow the hw atomic limits. (nha) v3.2: fix some docs inconsistencies (Ilia) Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: add CAPs to support HW atomic counters. (v3)Dave Airlie2017-11-1015-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left the CAP for atomic type extensible in case someone else has a variant on this sort of thing (freedreno maybe?) and needs to change it. This adds all the CAPs required to add support for those atomic counters, along with a related CAP for limiting the number of output resources. I'd like to land this and the st patch then I can start to upstream the evergreen support for these and other GL4.x features. v2: drop the ATOMIC_COUNTER_MODE cap, just use the return from the HW counters. If 0 we use the current mode. v3: fix some rebase errors (Gert Wollny) Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-By: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/query: drop rest of vi workaround code.Dave Airlie2017-11-102-37/+13
| | | | | | | | This isn't needed in r600 anymore. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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