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* android: nvir/gv100: update sources in Makefile.sourcesMauro Rossi2020-06-121-0/+6
| | | | | | | | | | | | | | | Fixes the following building errors: FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so ... ld.lld: error: undefined symbol: nv50_ir::getTargetGV100(unsigned int) ... ld.lld: error: undefined symbol: nv50_ir::getTargetGV100(unsigned int) clang-9: error: linker command failed with exit code 1 (use -v to see invocation) Fixes: 78103abe ("nvir/gv100: initial support") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* iris/icl+: Report same caching domain as main surface for clear color BO.Francisco Jerez2020-06-111-2/+1
| | | | | | | | | | | | | | | | | Even though the clear color BO is bound as a read-only buffer, report the same caching domain as the main BO in use_surface() (typically IRIS_DOMAIN_RENDER_WRITE) in order to avoid ping-ponging back and forth between IRIS_DOMAIN_RENDER_WRITE and IRIS_DOMAIN_OTHER_READ, which leads to increased stall-at-pixel-scoreboard synchronization between draw calls. Fixes a 5%-10% FPS regression in some benchmarks spotted on ICL. Reported-by: Clayton Craft <[email protected]> Fixes: eb5d1c27227302167d299 "iris: Annotate all BO uses with domain and sequence number information." Closes: #3097 Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5411>
* iris: Better handle metadata in NIR passesJason Ekstrand2020-06-111-2/+8
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5171>
* gallivm/sample: fix texel type for stencil 8-bitDave Airlie2020-06-111-1/+1
| | | | | | | | | | This has to be unsigned, so clamping works properly for border colors. Fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_uint_stencil Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* gallivm/conv: enable conversion min code. (v2)Dave Airlie2020-06-111-2/+4
| | | | | | | | | | | | I'm not sure why this code was if (0), but if (1) for it fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_float_color This test expects +inf to get mapped to 255 and -inf to 0, both values were ending up at 0. v2: also enable in the SSE paths Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* gallivm/format: convert unsigned values to float properly.Dave Airlie2020-06-111-1/+1
| | | | | | | | | | | | This fixes: dEQP-GLES31.functional.draw_indirect.random.2 which ends up with 3x32-bit USCALED values going down this path some of which have the top bit set, and end up converted to signed float instead of unsigned float values. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* llvmpipe: fix subpixel bits reporting.Dave Airlie2020-06-111-0/+2
| | | | | | | This fixes some vulkan tests later. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* gallivm/nir: add group barrier supportDave Airlie2020-06-111-0/+1
| | | | | | | | Fixes crash in dEQP-GLES31.functional.synchronization.inter_invocation.image_write_read Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* draw/gs: add more info to debugging.Dave Airlie2020-06-111-3/+4
| | | | | | | | adds invocations and vertex streams to default off debug, fixes compile as well due to missing , Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* draw/gs: fix emitting inactive primitives crashDave Airlie2020-06-112-1/+6
| | | | | | | | | | | | Fixes dEQP-GLES31.functional.geometry_shading.emit.line_strip_emit_1_end_1 This test only emits 1 primitive, but the stores don't respect the current mask, which might only have one lane active, for that single primitive. Also fix the final emit path to use the emitted_mask rather than the current execution mask. Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5379>
* freedreno/a6xx: Fix clip_halfz support.Eric Anholt2020-06-101-1/+4
| | | | | | Same bit as on other gens, apparently it just got missed on this one. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5419>
* nvc0: initial support for tu1xxBen Skeggs2020-06-1013-41/+1126
| | | | | | | | | v2: - add proper method definitions Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvc0: initial support for gv100Ben Skeggs2020-06-1013-35/+578
| | | | | | | | | | v2: - remove unnecessary MAX2() - add proper method definitions Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvc0: remove hardcoded blitter vertprogBen Skeggs2020-06-101-73/+39
| | | | | | | | I don't really feel like writing SM70 SASS by hand... Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvc0: move setting of entrypoint for a shader stage to a functionBen Skeggs2020-06-103-14/+23
| | | | | | | | GV100 requires something different, cleaner to move this to a single place. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvc0: use NVIDIA headers for GP100- compute QMDBen Skeggs2020-06-107-141/+880
| | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvc0: use NVIDIA headers for GK104->GM2xx compute QMDBen Skeggs2020-06-108-160/+1085
| | | | | | | | | | | v2: - add header debug_printf(), and indent the output v3: - rename one of the helper macros Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/gv100: enable support for tu1xxBen Skeggs2020-06-102-0/+3
| | | | | | | | | SM75 has a bunch more stuff, but is otherwise backwards-compatible with SM70 SASS. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/gv100: initial supportBen Skeggs2020-06-1014-19/+3683
| | | | | | | | | | | | | | | | | v2: - add TargetGV100::isBarrierRequired() for OP_BREV - use NV50_IR_SUBOP_LOP3_LUT() convenience macro where it makes sense - separated out nir_lower_idiv into its own commit - make use of the shared function to generate compiler options - disable lower_fpow, nir's lowering is broken v3: - use replaceCvt() instead of custom NEG/ABS/SAT lowering v4: - remove WAR from peephole, not needed now we're using replaceCvt() Signed-off-by: Ben Skeggs <[email protected]> Acked-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir/gm107: switch off lower_extract_wordBen Skeggs2020-06-101-1/+1
| | | | | | | | We can use PRMT here. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir/gm107: switch off lower_extract_byteBen Skeggs2020-06-101-1/+1
| | | | | | | | We can use PRMT here. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir/gm107: turn on nir_lower_extract64Ben Skeggs2020-06-101-0/+1
| | | | | | | | | About to disable lowering for extract_byte/word in favour of a better local implementation, but still need lowering for 64-bit versions. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir/gm107: split nir shader compiler options from gf100Ben Skeggs2020-06-101-0/+4
| | | | | | | | | | | We can enable some more things here vs earlier GPUs. v2: - make use of the shared function to generate compiler options Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/gm107: separate out header for sched data calculatorBen Skeggs2020-06-102-150/+157
| | | | | | | | SM70 code emitter will want to reuse this. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/gm107: replace SHR+AND+AND with PRMT+PRMT in PFETCH loweringBen Skeggs2020-06-101-3/+2
| | | | | | | | This is more SM70-friendly. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/gm107: implement OP_PERMTBen Skeggs2020-06-101-0/+31
| | | | | | | | | PFETCH lowering will be changed to use this as it's more SM70-friendly, and this will also allow us to implement extract_byte/word opcodes. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: use nir_lower_idivBen Skeggs2020-06-101-0/+5
| | | | | | | | | | | | | | NIR provides a common implementation of this so we don't need to use a hand-written built-in library. v2: - use idiv_precise instead Especially important on SM70 where we don't have an assembler. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: nir expects the shift amount to wrap, rather than clampBen Skeggs2020-06-101-0/+4
| | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_urorBen Skeggs2020-06-101-0/+10
| | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_urolBen Skeggs2020-06-101-0/+10
| | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_extract_i16Ben Skeggs2020-06-101-0/+8
| | | | | | | | | | | v2: - use getSSA() instead of getScratch() v3: - fix whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_extract_u16Ben Skeggs2020-06-101-0/+8
| | | | | | | | | | | v2: - use getSSA() instead of getScratch() v3: - fix whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_extract_i8Ben Skeggs2020-06-101-0/+8
| | | | | | | | | | | v2: - use getSSA() instead of getScratch() v3: - fix whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: implement nir_op_extract_u8Ben Skeggs2020-06-101-0/+8
| | | | | | | | | | | v2: - use getSSA() instead of getScratch() v3: - fix whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: turn on lower_rotateBen Skeggs2020-06-101-1/+1
| | | | | | | | This isn't implemented, and won't be for GPUs that don't support SHF. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: flesh out optionsBen Skeggs2020-06-101-0/+17
| | | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: move nir options to codegenBen Skeggs2020-06-103-63/+89
| | | | | | | | | | | | These seem to make more sense living with the compiler. v2: - use a shared function to generate the per-chipset structs - remove nir.h include from header, not needed Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: fix fragment program output when using MRTBen Skeggs2020-06-101-1/+5
| | | | | | | | | v2: - use BITFIELD64_BIT() Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir/nir: use component helpers instead of insn->num_componentsKarol Herbst2020-06-101-15/+16
| | | | | | | | | | | We have nir_intrinsic_dest_components and nir_intrinsic_src_components which handle all the corner cases. Fixes a bunch of regressions like front_face stuff. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: run replaceZero() before replaceCvt()Ben Skeggs2020-06-101-3/+3
| | | | | | | | replaceCvt() will miss some cases otherwise. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: add constant folding for OP_PERMTBen Skeggs2020-06-101-0/+9
| | | | | | | | | | | | Important for SM70 INSBF/EXTBF lowering, as these can can often be eliminated completely. v2: - skip CF when subOp is set Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_FINALBen Skeggs2020-06-103-3/+5
| | | | | | | | Required to support SM70 GS. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_SGXTBen Skeggs2020-06-104-2/+15
| | | | | | | | | | | Required for SM70 EXTBF lowering. v2: - added constant folding Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_BMSKBen Skeggs2020-06-105-4/+11
| | | | | | | | | | | | | | | This replaces the existing implementation without adding lowering for earlier GPUs. The reason for this is because the existing code isn't at all correct, and it also can't be hit anyway. Will be required to support SM70 lowering passes. v2: - fixup source selection Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_SHFBen Skeggs2020-06-103-3/+12
| | | | | | | | | | | | | | | | | We already use a hack from NVC0LegalizeSSA::handleShift() on GK110 and newer which encodes SHF into the existing SHL/SHR opcodes, but there's a couple of problems with it: - LO/HI are swapped in one of the directions, which is very confusing. - The initial SM70 code will emit this from NIR->NVIR, and using the existing encodings will confuse the optimisation passes. As I want to limit the impact on other GPUs from the initial bring-up of Volta/Turing, let's add an explicit representation of SHF in the IR. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_BREV with lowering to EXTBF_REV for current GPUsBen Skeggs2020-06-108-12/+29
| | | | | | | | SM70 has this instruction, but no BFE. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_WARPSYNCBen Skeggs2020-06-103-0/+5
| | | | | | | | Will be required to support SM70. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: introduce OP_LOP3_LUTBen Skeggs2020-06-104-3/+22
| | | | | | | | | | | Will be required to support SM70, but is also available on earlier GPUs. v2: - add convenience macro suggested by Karol Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* nvir: bump max encoding size of instructionsBen Skeggs2020-06-102-2/+2
| | | | | | | | SM70 SASS is encoded into 16 bytes. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5377>
* gallium/hud: do not specify potentially invalid depth-rangeErik Faye-Lund2020-06-101-1/+1
| | | | | | | | | | | | Setting the depth-scale to 1 while leaving the depth-translation at 0 means our near-plane is at -1 in OpenGL semantics, which is out-of-range on some drivers. In particular, Zink has this limitation. But since we'll only pass a zero z in here anyway, we might as well multiply it by zero, and get the same result. This avoids the problem. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5408>
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