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* softpipe: Use mag texture filter also for clamped lod == 0Gert Wollny2019-04-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Follow the spec when selecting the magnification filter (OpenGL 4.5, section 8.14): If λ(x, y) is less than or equal to the constant c (see section 8.15) the texture is said to be magnified; While we're here also silence a potential warning about implicit float to double conversion. v2: Update commit message to contain a reference to the spec as pointed out by Eric. Fixes a number of dEQP GLES2 and GLES3 test out of: dEQP-GLES2.functional.texture.filtering.* dEQP-GLES2.functional.texture.vertex.2d.filtering.* dEQP-GLES3.functional.texture.vertex.*.filtering.* dEQP-GLES3.functional.texture.filtering.* dEQP-GLES3.functional.texture.shadow.2d.* Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* iris: handle aux properly in iris_resource_get_handleTapani Pälli2019-04-041-0/+8
| | | | | | | | | Disable aux when resource seen the first time and EXPLICIT_FLUSH not being set. This fixes issues seen when launching Xorg and CCS_E getting utilized. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* v3d: Don't try to use the TFU blit path if a scissor is enabled.Eric Anholt2019-04-041-1/+2
| | | | | | | | We'll need to do a render-based blit for scissors, since the TFU (as seen in this conditional) can only update a whole surface. Fixes: 976ea90bdca2 ("v3d: Add support for using the TFU to do some blits.") Fixes piglit fbo-scissor-blit.
* v3d: Bump the maximum texture size to 4k for V3D 4.x.Eric Anholt2019-04-043-2/+29
| | | | | | | 4.1 and 4.2 both have the same 16k limit, but it I'm seeing GPU hangs in the CTS at 8k and 16k. 4k at least lets us get one 4k display working. Cc: [email protected]
* v3d: Add support for handling OOM signals from the simulator.Eric Anholt2019-04-043-14/+78
| | | | | | I have v3d allocating enough initial allocation memory that we've been passing tests without it, but to match kernel behavior more it would be good to actually exercise the OOM path.
* ddebug: add compute functions to help hang detectionDave Airlie2019-04-051-2/+21
| | | | Reviewed-by: Marek Olšák <[email protected]>
* iris: avoid use after free in shader destructionDave Airlie2019-04-051-7/+49
| | | | | | | | | | | While playing with compute shaders, I was getting a random crash, noticed that bind_state was using the old shader info for comparision, but gallium allows the shader to be deleted while bound, so this could lead to a use after free. This can't happen using the cso cache. As it tracks all of this. Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: set exact shader buffer read/write usage in CSMarek Olšák2019-04-046-24/+41
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add writable_bitmask parameter into set_shader_buffersMarek Olšák2019-04-0417-25/+48
| | | | | | | to indicate write usage per buffer. This is just a hint (it will be used by radeonsi). Reviewed-by: Timothy Arceri <[email protected]>
* iris: Fix assert when using vertex attrib without buffer bindingDanylo Piliaiev2019-04-041-1/+2
| | | | | | | | | | | | | The GL 4.5 spec says: "If any enabled array’s buffer binding is zero when DrawArrays or one of the other drawing commands defined in section 10.4 is called, the result is undefined." The result is undefined but it should not crash. Fixes: gl-3.1-vao-broken-attrib Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: move iris_flush_resource so we can call it from get_handleTapani Pälli2019-04-041-15/+15
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Save/restore MI_PREDICATE_RESULT, not MI_PREDICATE_DATA.Kenneth Graunke2019-04-043-8/+8
| | | | | | | | MI_PREDICATE_DATA is an intermediate storage for the MI_PREDICATE command's calculations - it holds the result of the subtraction when the compare operation is SRCS_EQUAL or DELTAS_EQUAL. But the actual result of the predication is MI_PREDICATE_RESULT, which is what we want to copy from the render context to the compute context.
* simplify LLVM version string printingEric Engestrom2019-04-042-18/+9
| | | | | | | Figure it out once in the build system, then just use that all over the place. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/u_dump: util_dump_sampler_view: Dump u.tex.first_levelGuido Günther2019-04-041-1/+1
| | | | | | | Dump u.tex.first_level instead of dumping u.tex.last_level twice. Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: ddebug: Add missing fence related wrappersGuido Günther2019-04-042-0/+37
| | | | | | | | | | | | | | Without that `GALLIUM_DDEBUG=always kmscube -A` would segfault like #0 0x0000000000000000 in () #1 0x0000ffffa72a3c54 in dri2_get_fence_fd (_screen=0xaaaaed4f2090, _fence=0xaaaaed9ef880) at ../src/gallium/state_trackers/dri/dri_helpers.c:140 #2 0x0000ffffa8744824 in dri2_dup_native_fence_fd (drv=0xaaaaed5010c0, disp=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/drivers/dri2/egl_dri2.c:3050 #3 0x0000ffffa87339b8 in eglDupNativeFenceFDANDROID (dpy=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/main/eglapi.c:2107 #4 0x0000aaaabd29ca90 in () #5 0x0000aaaabd401000 in () Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* gallium/hud: fix rounding error in nic bps computationEric Engestrom2019-04-041-2/+2
| | | | | | | | While at it, fix typo in "rounding error" :P Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: prevent buffer overflowEric Engestrom2019-04-043-6/+6
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: fix memory leaksEric Engestrom2019-04-043-2/+7
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for displayable DCC for multi-RB chipsMarek Olšák2019-04-047-4/+253
| | | | A compute shader is used to reorder DCC data from aligned to unaligned.
* radeonsi: add support for displayable DCC for 1 RB chipsMarek Olšák2019-04-043-4/+84
| | | | This is the simpler codepath - just disable RB and pipe alignment for DCC.
* radeonsi: add ability to bind images as image buffersMarek Olšák2019-04-042-3/+8
| | | | so that we can bind DCC (texture) as an image buffer.
* radeonsi/gfx9: add support for PIPE_ALIGNED=0Marek Olšák2019-04-044-12/+30
| | | | | | Needed by displayable DCC. We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
* iris: move variable to the scope where it is being usedTapani Pälli2019-04-041-1/+1
| | | | | | | | | iris_upload_border_color is passed a pointer which points to variable that is introduced in a different scope. CID: 1444296 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* panfrost: Size tiled temp buffers correctlyAlyssa Rosenzweig2019-04-043-8/+13
| | | | | | | | This should lower transient memory usage and improve performance slightly (due to less memory to malloc/free, better cache locality, etc). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect box->width in tiled storesAlyssa Rosenzweig2019-04-043-4/+6
| | | | | | | This fixes a regression uploading partial tiled textures introduced sometime during the cubemap series. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Cleanup some indirection in pan_resourceAlyssa Rosenzweig2019-04-041-24/+21
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement system valuesAlyssa Rosenzweig2019-04-047-188/+229
| | | | | | | | | | | | | | | | | | This patch implements system values via specially-crafted uniforms. While we previously had an ad hoc system for passing the viewport into the vertex shader, this commit generalizes the system to allow for arbitrary system values to be added to both shader stages. While we're at it, we clean up uniform handling code (which was considerably muddied to handle the ad hoc viewport uniform). This commit serves as both a cleanup of the existing codebase and the precursor to new functionality, like implementing textureSize(). Concurrent with these changes is respecting the depth transform, which was not possible with the old fixed uniform system and here serves as a proof-of-correctness test (as well as justifying the NIR changes). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* virgl: also destroy all read-transfersErik Faye-Lund2019-04-032-2/+4
| | | | | | | | | | | | | | | For texture write-transfers, we either free them on the transfer-queue or right away. But for read-transfers, we currently only destroy them in case they used a temp-resource. This leads to occasional resource-leaks. Let's add a call to virgl_resource_destroy_transfer in the missing case. Do the same thing for buffers as well, but the logic is a bit easier to follow there. Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: f0e71b10888 ("virgl: use transfer queue") Reviewed-by: Gurchetan Singh <[email protected]>
* panfrost: Remove support for legacy kernelsAlyssa Rosenzweig2019-04-038-39/+8
| | | | | | | | | | | | | | Previously, there was minimal support for interoperating with legacy kernels (reusing kernel modules originally designed for proprietary legacy userspaces, rather than for upstream-friendly free software stacks). Now that the Panfrost kernel is stabilising, this commit drops the legacy code path. Panfrost users need to use a modern, mainline kernel supporting the Panfrost kernel driver from this commit forward. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* etnaviv: only try to construct scanout resource when on KMS winsysLucas Stach2019-04-031-1/+1
| | | | | | | | | | Trying to construct a scanout capable buffer will only ever work when when we are on top of a KMS winsys, as the render node isn't capable of allocating contiguous buffers. Tested-by: Marius Vlad <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: flush all pending contexts when accessing a resource with the CPULucas Stach2019-04-031-2/+8
| | | | | | | | | | | | | When setting up a transfer to a resource, all contexts where the resource is pending must be flushed. Otherwise a write transfer might be started in the current context before all contexts that access the resource in shared (read) mode have been executed. Fixes: 64813541d575 (etnaviv: fix resource usage tracking across different pipe_context's) Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Tested-By: Guido Günther <[email protected]>
* etnaviv: don't flush own context when updating resource useLucas Stach2019-04-031-1/+10
| | | | | | | | | | | | The context is self synchronizing at the GPU side, as commands are executed in order. We must not flush our own context when updating the resource use, as that leads to excessive flushing on effectively every draw call, causing huge CPU overhead. Fixes: 64813541d575 (etnaviv: fix resource usage tracking across different pipe_context's) Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: shrink struct etna_3d_stateChristian Gmeiner2019-04-032-23/+0
| | | | | | | Drop struct members which are only written to but never read from. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* virgl: close drm fd when destroying virgl screen.Lepton Wu2019-04-021-0/+1
| | | | | | | | This fd was create in virgl_drm_screen_create and should be closed in virgl_drm_screen_destroy. Signed-off-by: Lepton Wu <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* iris: Enable fast clears on gen8.Rafael Antognolli2019-04-021-2/+1
| | | | | | | Since we are now properly storing the clear color with SCS bits, we can now enable fast clears on gen8 too. Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add aux.sampler_usages.Rafael Antognolli2019-04-023-16/+34
| | | | | | | | | | | | | | We want to skip some types of aux usages (for instance, ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have multisampling) when sampling from the surface. Instead of checking for those cases while filling the surface state and leaving it blank, let's have a version of aux.possible_usages for sampling. This way we can also avoid allocating surface state for the cases we don't use. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Do not allocate clear_color_bo for gen8.Rafael Antognolli2019-04-022-6/+9
| | | | | | | | Since we are not using it for the clear color, there's no need to allocate it. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Manually apply fast clear color channel overrides.Rafael Antognolli2019-04-021-6/+16
| | | | | | | | | | | | At the fast clear time, the only swizzle we have available is actually the identity swizzle (which we use for most rendering). So the call to swizzle_color_value() becomes simply a no-op, and doesn't properly zero out the unused channels. We have to manually override those channels. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.Rafael Antognolli2019-04-021-10/+28
| | | | | | | | | | | | | | | | The swizzle for rendering surfaces is always identity. So when we are doing the fast clear, we don't have enough information to store the clear color OR'ed with the Shader Channel Select bits for the dword in the SURFACE_STATE. Instead of trying to patch up the SURFACE_STATE correctly later, by reading the color from the clear color state buffer and then doing all the operations to store it, let's just re-emit the whole SURFACE_STATE. That should make things way simpler on gen8, and we can still use the clear color state buffer for gen9+. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Only update clear color for gens 8 and 9.Rafael Antognolli2019-04-021-1/+10
| | | | | | | | | Newer gens can read it directly. Also properly skip updating the ISL_AUX_USAGE_NONE surface. Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state." Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: don't use PFP_SYNC_ME with compute-only contextsMarek Olšák2019-04-021-1/+1
| | | | | | | | | | Compute rings don't have PFP. Fixes: a1378639ab1 "radeonsi: always use compute rings for clover on CI and newer (v2)" Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Jan Vesely <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* virgl: define MAX_VERTEX_STREAMS based on availability of TF3Gert Wollny2019-04-022-1/+3
| | | | | | | | | | Since with gles hosts we lie about the GLSL feature level it is better to set the number of streams based on actual hosts capabilities. v2: Make use of feature check level to avoid regressions. Signed-off-by: Gert Wollny <[email protected]> Reviewed-By: Reviewed-by: Gurchetan Singh <[email protected]>
* softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADDGert Wollny2019-04-022-10/+18
| | | | | | | | | | | | | | This enables the following piglits with PASS: nv_shader_atomic_float/execution/ shared-atomicadd-float shared-atomicexchange-float ssbo-atomicadd-float ssbo-atomicexchange-float v2: Minimize the patch by using type punning (Eric Anholt) Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* virgl: stricter usage of compressed 3d texturesErik Faye-Lund2019-04-021-0/+6
| | | | | | | | | | | | | Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc, EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture, S3_s3tc or EXT_texture_compression_s3tc specifications. So let's not allow any of those compressed 3d-textures at all. It's not going to work once it hits the OpenGL driver in virglrenderer. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: do not allow compressed formats for buffersErik Faye-Lund2019-04-021-0/+3
| | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* iris: Adapt to variable ppGTT sizeChris Wilson2019-04-011-1/+20
| | | | | | | | | Not all hardware is made equal and some does not have the full complement of 48b of address space. Ask what the actual size of virtual address space allocated for contexts, and bail if that is not enough to satisfy our static partitioning needs. Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: implement ARB/KHR_parallel_shader_compile callbacksMarek Olšák2019-04-011-0/+31
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* gallium: implement ARB/KHR_parallel_shader_compileMarek Olšák2019-04-011-0/+13
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* radeonsi: fix assertion failure by using the correct typeMarek Olšák2019-04-011-1/+1
| | | | | | | | | | src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband: Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] && vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed. The comparison was unsigned, so negative maxx or maxy would fail. Fixes: 3c540e0a7488 "radeonsi: Fix guardband computation for large render targets"
* radeon/vcn/vp9: search the render target from the whole listLeo Liu2019-04-011-1/+1
| | | | | | | | | | | | | The number of render targets could be more than max of references, so we search the full list of the render pictures for the current render target index https://bugs.freedesktop.org/show_bug.cgi?id=109648 Signed-off-by: Leo Liu <[email protected]> Tested-by: James Zhu <[email protected]> Acked-by: James Zhu<[email protected]> Cc: <[email protected]>
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