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* lima: introduce a struct describing texture descriptorVasily Khoruzhick2019-08-083-56/+150
| | | | | | | | | | | | | Use a struct with bitfields to construct texture descriptor instead of poking bits in array of uint32_t. It improves code readability and makes it easier to experiment with unknown fields. Also fix mipmapping while we're at it - Utgard can have up to 13 levels, but 64 bytes is enough only for 10. Calculate descriptor size dynamically to account extra levels if we need them. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: add texel format tableVasily Khoruzhick2019-08-083-51/+53
| | | | | | | | | Introduce a table for supported texel formats and use it to check whether format is supported and for converting pipe format to lima texel format. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* virgl: check scanout maskGurchetan Singh2019-08-082-0/+7
| | | | | | | | | Otherwise, virgl will report renderable or texturable formats as also scan-out formats. v2: drop host feature check (@kusma) Reviewed-by: Erik Faye-Lund <[email protected]>
* virgl: fixup_readback_format --> fixup_formatsGurchetan Singh2019-08-081-8/+7
| | | | | | | This function is generalizable. Suggested-by: Erik Faye-Lund <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]>
* virgl: access caps in a less verbose way in virgl_is_format_supportedGurchetan Singh2019-08-081-9/+9
| | | | Reviewed-by: Erik Faye-Lund <[email protected]>
* meson: define ETIME to ETIMEDOUT if not presentGreg V2019-08-081-3/+0
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* lima: Fix Android.mkRoman Stratiienko2019-08-082-4/+18
| | | | | | | | | | | | | | | 1. Update LOCAL_SRC_FILES according to commit 54434fe67068 ("lima/gpir: Rework the scheduler"). 2. Add libpanfrost_shared.a dependency. 3. Generate lima_nir_algebraic.c with Android.mk Fixes Android build error introduced by commit 5adfc8602c63 ("lima/ppir: move sin/cos input scaling into NIR") Signed-off-by: Roman Stratiienko <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Acked-by: Qiang Yu <[email protected]>
* anv,i965,iris: deduplicate setting of total_sharedRhys Perry2019-08-081-2/+0
| | | | | | | | v5: add patch Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: avoid warning on WindowsErik Faye-Lund2019-08-081-1/+1
| | | | | | | | | | On Windows, p_atomic_inc_return returns an unsigned long long rather than the type the pointer refers to, so let's make sure we cast the result to the right type. Otherwise, we'll trigger a warning about the wrong format-string for the type. Signed-off-by: Erik Faye-Lund <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* etnaviv: remember data offset into BOLucas Stach2019-08-081-0/+1
| | | | | | | | | | Imported resources might not start at offset 0 into the buffer object. Make sure to remember the offset that is provided with the handle on import. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* swr/rasterizer: modernize thread TLBJan Zielinski2019-08-0814-30/+135
| | | | Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: Refactor events collection mechanismJan Zielinski2019-08-0810-439/+382
| | | | | | Several improvements and cleanups in events and statstics mechanisms Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: improvements in simdlibJan Zielinski2019-08-0817-492/+49
| | | | | | | | | | | | | 1. fix build issues with MSVC 2019 compiler The MSVC 2019 compiler seems to have an issue with optimized code-gen when using the _mm256_and_si256() intrinsic. Only disable use of integer vpand on buggy versions MSVC 2019. Otherwise allow use of integer vpand intrinsic. 2. Remove unused vec/matrix functionality Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: Events are now grouped and enabled by knobsJan Zielinski2019-08-0815-202/+372
| | | | | | | | | | | | | All events are now grouped as follows: -Framework (i.e. ThreadStart) [always ON] -Api (i.e. SwrSync) [always ON] -Pipeline [default ON] -Shader [default ON] -SWTag [default OFF] -Memory [default OFF] Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: do not mark tiles dirty until actually renderedJan Zielinski2019-08-0813-8/+72
| | | | Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: enable size accumulation in mem statsJan Zielinski2019-08-0811-104/+128
| | | | | | Small refactoring is also performed Reviewed-by: Alok Hota <[email protected]>
* swr/rasterizer: enable using AOS vertex data formatJan Zielinski2019-08-083-21/+81
| | | | Reviewed-by: Alok Hota <[email protected]>
* v3d: handle wait requirement when retrieving query results correctlyIago Toral Quiroga2019-08-081-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: use the GPU to record primitives written to transform feedbackIago Toral Quiroga2019-08-087-16/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can use the PRIMITIVE_COUNTS_FEEDBACK packet to write various primitive counts to a buffer, including the number of primives written to transform feedback buffers, which will handle buffer overflow correctly. There are a couple of caveats with this: Primitive counters are reset when we emit a 'Tile Binning Mode Configuration' packet, which can happen in the middle of a primitives query, so we need to read the buffer when we submit a job and accumulate the counts in the context so we don't lose them. We also need to do the same when we switch primitive type during transform feedback so we can compute the correct number of recorded vertices from the number of primitives. This is necessary so we can provide an accurate vertex count for draw from transform feedback. v2: - When computing the number of vertices for a primitive, pass in the base primitive, since that is what the hardware will count. - No need to update primitive counts when switching primitive types if the base primitives are the same. - Log perf warning when mapping the primitive counts BO for readback (Eric). - Only emit the primitive counts packet once at job end (Eric). - Use u_upload mechanism for the primitive counts buffer (Eric). - Use the XML to generate indices into the primitive counters buffer (Eric). Fixes piglit tests: spec/ext_transform_feedback/overflow-edge-cases spec/ext_transform_feedback/query-primitives_written-bufferrange spec/ext_transform_feedback/query-primitives_written-bufferrange-discard spec/ext_transform_feedback/change-size base-shrink spec/ext_transform_feedback/change-size base-grow spec/ext_transform_feedback/change-size offset-shrink spec/ext_transform_feedback/change-size offset-grow spec/ext_transform_feedback/change-size range-shrink spec/ext_transform_feedback/change-size range-grow spec/ext_transform_feedback/intervening-read prims-written Reviewed-by: Eric Anholt <[email protected]>
* gallium/util: add a helper to compute vertex count from primitive countIago Toral Quiroga2019-08-083-1/+91
| | | | | | | | v2: - Only compute vertex counts for base primitives. - Add a unit test (Eric) Reviewed-by: Eric Anholt <[email protected]>
* v3d: be more explicit about the query types supportedIago Toral Quiroga2019-08-081-3/+11
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: generate packet unpack functionsIago Toral Quiroga2019-08-081-0/+10
| | | | | | | | | These were not being compiled because of the lack of __gen_unpack_address. v2: - Shift raw address correctly (Eric). Reviewed-by: Eric Anholt <[email protected]>
* panfrost: Print errors from kernelTomeu Vizoso2019-08-081-5/+5
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Mark buffers as PANFROST_BO_HEAPTomeu Vizoso2019-08-081-0/+6
| | | | | | | | | | | | What we call GROWABLE in Mesa corresponds to the HEAP BO flag in the kernel. These buffers cannot be memory mapped in the CPU side at the moment, so make sure they are also marked INVISIBLE. This allows us to allocate a big heap upfront (16MB) without actually reserving space unless it's needed. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Mark BOs as NOEXECTomeu Vizoso2019-08-083-2/+10
| | | | | | | | | Unless a BO has the EXECUTABLE flag, mark it as NOEXEC. v2: - Rework version detection (Alyssa). Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Take into account flags when looking up in the BO cacheTomeu Vizoso2019-08-083-3/+5
| | | | | | | | | | | | This will be useful right now so we avoid retrieving a non-executable buffer when a executable one is needed. As we support more flags, this logic will need to be extended to consider the different trade-offs to be made when matching BO specifications to BOs in the cache. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allocate shaders in their own BOsTomeu Vizoso2019-08-087-32/+61
| | | | | | | | | | | | | | | | | | | | | Instead of all shaders being stored in a single BO, have each shader in its own. This removes the need for a 16MB allocation per context, and allows us to place transient blend shaders in BOs marked as executable (before they were allocated in the transient pool, which shouldn't be executable). v2: - Store compiled blend shaders in a malloc'ed buffer, to avoid reading from GPU-accessible memory when patching (Alyssa). - Free struct panfrost_blend_shader (Alyssa). - Give the job a reference to regular shaders when emitting (Alyssa). v3: - Split out the allocation flags change (Rob). Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* intel/perf: move perf-related constants to common locationMark Janes2019-08-071-0/+1
| | | | | | | | The perf subsystem needs several macro definitions that were duplicated in Iris and i965 headers. Place these macros within perf, if the perf implementation contains the only references to the values. Reviewed-by: Kenneth Graunke <[email protected]>
* nvc0: fix program dumping, use _debug_printfIlia Mirkin2019-08-071-6/+6
| | | | | | | | | This debug situation is unforunate. debug_printf only does something with DEBUG set, but in practice all that needs to be moved to !NDEBUG. For now, use _debug_printf which always prints. However the whole function is guarded by !NDEBUG. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for ATOMC_WRAP TGSI operationsIlia Mirkin2019-08-072-1/+11
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: redefine ATOMINC_WRAP to be more hardware-friendlyIlia Mirkin2019-08-072-13/+1
| | | | | | | | Both AMD and NVIDIA hardware define it this way. Instead of replicating the logic everywhere, just fix it up in one place. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: limit DPBB context_states_per_bin batches when using gfx9 workaroundPierre-Eric Pelloux-Prayer2019-08-071-1/+5
| | | | | | | | It seems that using 'context_states_per_bin = 1' for DPBB fixes the reported issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110214 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: reduce DPBB persistent_states_per_bin value for APUsPierre-Eric Pelloux-Prayer2019-08-071-1/+2
| | | | | | | | Fixes some reported GPU hangs on RAVEN. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111231 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix typo in DPBB register fieldPierre-Eric Pelloux-Prayer2019-08-071-1/+4
| | | | | | | Also only set FLUSH_ON_BINNING_TRANSITION for GPU families that needs it (matches what si_emit_dpbb_disable is doing). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix S_028C48_MAX_ALLOC_COUNT valuePierre-Eric Pelloux-Prayer2019-08-071-1/+1
| | | | | | This field uses "value minus 1" encoding. Reviewed-by: Marek Olšák <[email protected]>
* etnaviv: drop struct etna_3d_stateChristian Gmeiner2019-08-073-17/+1
| | | | | | | Also drop #if 0 code block. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* meson,i965: Link with android deps when building for android.Bas Nieuwenhuizen2019-08-071-2/+2
| | | | | | | | | | | The DBG marco in brw_blorp.c ends up calling an android log function: error: undefined reference to '__android_log_print' v2: On suggestion from Lionel, hang the Android dependency onto a new libintel_common dependency. Reviewed-by: Lionel Landwerlin <[email protected]>
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-071-0/+1
| | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: 3f6b3d9db72 ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE") Reviewed-by: Marek Olšák <[email protected]>
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-071-0/+1
| | | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: a677799e51a ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding cap") Reviewed-by: Marek Olšák <[email protected]>
* clover: Fix build after clang r367864Jan Vesely2019-08-061-2/+8
| | | | | | | | v2: Drop special case of llvm-9 Signed-off-by: Jan Vesely <[email protected]> Acked-by: Dieter Nützel <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Aaron Watry <[email protected]>
* mesa: freedreno: Android.registers.mk: Fix up register xml.h file generationJohn Stultz2019-08-072-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The current Androdi.registers.mk file causes build failures that look like: FAILED: external/mesa3d/src/freedreno/Android.registers.mk:49: error: implicit rules are obsolete: out/target/product/linaro_db845c/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/%.xml.h Caused by the following Android build rule change: https://android.googlesource.com/platform/build/+/HEAD/Changes.md#implicit_rules I tried to replace this with something similar to the static pattern suggested in the URL above, but ended up getting all the xml.h files generated using only the first a2xx.xml source file. So I've fallen back to explicitly defining the make rules for each. Additionally, we needed to provide the proper LOCAL_EXPORT_C_INCLUDE_DIRS and add the defined static library to the components that depend on the register headers. Acked-by: Eric Anholt <[email protected]> Signed-off-by: John Stultz <[email protected]>
* mesa: Add ir3/ir3_nir_imul.c generation to Android.mkJohn Stultz2019-08-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | With current master we're seeing build failures with AOSP: error: undefined symbol: ir3_nir_lower_imul This is due to the ir3_nir_imul.c file not being generated in the Android.mk files. This patch simply adds it to the Android build, after which thigns build and book ok on db410c. Cc: Rob Clark <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Amit Pundir <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: Alistair Strachan <[email protected]> Cc: Greg Hartman <[email protected]> Cc: Tapani Pälli <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: John Stultz <[email protected]>
* panfrost: Take into account a index_bias for glDrawElementsBaseVertex callsRohan Garg2019-08-061-9/+9
| | | | | | | | | | | | | | Midgard does not accept a index_bias directly and relies instead on a bias correction offset (offset_bias_correction) in order to calculate the unbiased vertex index. We need to make sure we adjust offset_start and vertex_count in order to take into account the index_bias as required by a glDrawElementsBaseVertex call and then supply a additional offset_bias_correction to the hardware. Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* mesa/gallium: add dric option to allow overriding GL vendor stringTimothy Arceri2019-08-073-0/+9
| | | | | | | Will be used in the following patch. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551
* tgsi_to_nir: add a few needed double opcodesMarek Olšák2019-08-061-0/+6
| | | | | | | | | for internal radeonsi shaders v2 (Connor): - Split out prep work from adding opcodes, and rewrite the former Reviewed-by: Marek Olšák <[email protected]>
* tgsi_to_nir: implement a few needed 64-bit integer opcodesMarek Olšák2019-08-061-0/+5
| | | | | | | | | | for internal radeonsi shaders v2 (Connor): - Split this out from the prep work, and rework the former - Add support for U64SNE Reviewed-by: Marek Olšák <[email protected]>
* ttn: Prepare for 64-bit sources and destinationsConnor Abbott2019-08-061-5/+29
| | | | | | v2: Properly handle 32->64 bit conversions Reviewed-by: Marek Olšák <[email protected]>
* ttn: Use 1-bit NIR comparison opcodesConnor Abbott2019-08-061-24/+19
| | | | | | | | | We shouldn't be using the versions that output a 32-bit boolean, since nir_opt_algebraic won't optimize them as well. Drivers will lower these to the 32-bit versions after optimizing, if appropriate. Also, this will make implementing 64-bit comparisons easier. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable EXT_shader_image_load_storePierre-Eric Pelloux-Prayer2019-08-061-0/+2
| | | | | | This depends on LLVM 10 because this needs https://reviews.llvm.org/D65283 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for nir atomic_inc_wrap/atomic_dec_wrapPierre-Eric Pelloux-Prayer2019-08-061-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
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