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* radeonsi: add support for tgsi ATOMDEC_WRAP / ATOMINC_WRAP opcodesPierre-Eric Pelloux-Prayer2019-08-061-0/+23
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_TGSI_ATOMINC_WRAP to indicate supportPierre-Eric Pelloux-Prayer2019-08-067-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add ATOMICINC_WRAP/ATOMICDEC_WRAP opcodePierre-Eric Pelloux-Prayer2019-08-065-2/+40
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx10: enable all CUs for GS if NGG is never usedMarek Olšák2019-08-061-2/+4
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: add global use_ngg and use_ngg_streamout flagsMarek Olšák2019-08-069-32/+41
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: remove an obsolete VGT_REUSE_OFF workaroundMarek Olšák2019-08-062-9/+0
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: disable LATE_ALLOC_GS on Navi14Marek Olšák2019-08-061-1/+8
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOCMarek Olšák2019-08-062-11/+12
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a bug workaround for NGG -> legacy transitionsMarek Olšák2019-08-062-2/+16
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a GE bug workaroundMarek Olšák2019-08-061-0/+18
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: set GE_CNTL for tessellation correctlyMarek Olšák2019-08-061-5/+11
| | | | | | | to match PAL Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: simplify NGG code in si_update_shadersMarek Olšák2019-08-061-9/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix input VGPRs for legacy VSMarek Olšák2019-08-062-8/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that rasterizer state != NULL and remove all NULL checkingMarek Olšák2019-08-067-17/+23
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that DSA state != NULL and remove all NULL checkingMarek Olšák2019-08-067-12/+19
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that blend state != NULL and remove all NULL checkingMarek Olšák2019-08-067-55/+52
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: DCC MSAA blending bug - include logic op, limit to Navi14 and olderMarek Olšák2019-08-062-2/+9
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: determine accurately whether logic op is enabledMarek Olšák2019-08-061-3/+5
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: skip draw calls with 0-sized index buffersMarek Olšák2019-08-061-0/+6
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/nir: lower PS inputs before scanning the shaderMarek Olšák2019-08-063-95/+86
| | | | | | | Lowering PS inputs can eliminate some of them, which messes up persp/linear barycentric coord usage info. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/nir: handle key.mono.u.ps.interpolate_at_sample_force_centerMarek Olšák2019-08-061-1/+4
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add missing prints into si_dump_shader_keyMarek Olšák2019-08-061-0/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: disable SDMA image copies on dGPUs to fix corruption in gamesMarek Olšák2019-08-061-1/+9
| | | | | Cc: 19.1 19.2 <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* iris: Handle vertex shader with window space positionDanylo Piliaiev2019-08-063-5/+44
| | | | | | | | | | Iris advertises support for PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION so let's actually implement it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110657 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* lima: fix pipe_debug_callback warningsErico Nunes2019-08-063-5/+5
| | | | | Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: move sin/cos input scaling into NIRVasily Khoruzhick2019-08-065-58/+69
| | | | | Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Increase BATCH_SZ to 64kBKenneth Graunke2019-08-061-1/+1
| | | | | This seems to improve performance by roughly ~1% across the board. Thanks to Rafael Antognolli and Dan Walsh for their help tuning.
* etnaviv: support 3D and 2D array texturesJonathan Marek2019-08-064-23/+74
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix 3d texture uploadJonathan Marek2019-08-066-30/+28
| | | | | | | | | | | Fix uploading of 3D textures and 2D array textures: * Remove asserts in BLT and RS checking z * Use box->z/box->depth in etna_copy_resource_box and CPU tile/untile * Track mip level depth and use it in etna_copy_resource Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: add alternative NIR compilerJonathan Marek2019-08-0612-37/+2388
| | | | | | | enable with ETNA_MESA_DEBUG=nir Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* etnaviv: prep for UBOsJonathan Marek2019-08-068-79/+71
| | | | | | | | | | | | | | | Allow UBO relocs and only emitting uniforms that are actually used. GC7000Lite has no address register, so upload uniforms to a UBO object to LOAD from. I removed the code to check for changes to individual uniforms and just reupload to entire uniform state when the state is dirty. I think there was very limited benefit to it and it isn't compatible with relocs. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: disasm: add dual16 bits, immediate decoding, and some opcodesJonathan Marek2019-08-061-59/+69
| | | | | | | | Also use structs from etnaviv_asm since they hold the same information. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: asm: new featuresJonathan Marek2019-08-063-11/+53
| | | | | | | | | | | * Dual16 bits * Halti5 disable multiple uniform src * write_mask compose * Halti2+ immediates Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: update headers from rnndbJonathan Marek2019-08-061-12/+4
| | | | | | | | Update to etna_viv commit f38ba2d. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* lima: add summary report for shader-dbErico Nunes2019-08-0610-6/+80
| | | | | | | | | | | | | | Very basic summary, loops and gpir spills:fills are not updated yet and are only there to comply with the strings to shader-db report.py regex. For now it can be used to analyze the impact of changes in instruction count in both gpir and ppir. The LIMA_DEBUG=shaderdb setting can be useful to output stats on applications other than shader-db. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima: add support for debug callbackErico Nunes2019-08-062-0/+15
| | | | | | | | This adds support for glDebugMessageCallback which is required to support shader-db reports. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* panfrost/ci: Remove two tests from list of failuresTomeu Vizoso2019-08-061-2/+0
| | | | | | | | These tests have been fixed by: b514f411837b ("glcpp: use pre-expansion line number for __LINE__") Signed-off-by: Tomeu Vizoso <[email protected]>
* st/dri: Move dri2_format_mapping table and it's accessors from dri2.c to ↵Jon Turney2019-08-063-213/+223
| | | | | | | | | dri_helpers.c 8af1990a exposed dri2_get_mapping_by_fourcc() in dri_helpers.h, so it could be used by dri_get_egl_image(), but didn't move it. This breaks the build in the with_dri=false case (e.g. when building for a target which doesn't have libdrm, so swrast is only dri driver built)
* tgsi_to_nir: fix nir_gather_ssa_types for TGSI->NIR shadersJonathan Marek2019-08-051-5/+13
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-By: Timur Kristóf <[email protected]>
* lima/ppir: enable lower_vector_cmp to lower fall_equalErico Nunes2019-08-051-0/+1
| | | | | Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* lima: re-run nir_opt_algebraic after int loweringErico Nunes2019-08-051-0/+15
| | | | | | | | | nir_lower_int_to_float is currently only meant to run once, and some ops must be lowered after being converted from int ops to be implementable, so re-run nir_opt_algebraic after lowering ints to floats. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* panfrost: Add app blacklistAlyssa Rosenzweig2019-08-051-2/+16
| | | | | | | | | | | | In preparation for an initial 19.2 release, add a blacklist for apps known to be buggy under Panfrost to protect users. Panfrost is NOT a conformant implementation at this time. Distros: please do not revert this patch. If blacklisted apps are run using Panfrost, dragons will bite you. Thanks :) Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Tomeu Vizoso <[email protected]>
* iris: Fix bad external BO hash table and zombie list interactionsKenneth Graunke2019-08-051-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A while ago, we started deferring GEM object closure and VMA release until buffers were idle. This had some unforeseen interactions with external buffers. We keep imported buffers in hash tables, so if we have repeated imports of the same GEM object, we map those to the same iris_bo structure. This is critical for several reasons. Unfortunately, we broke this assumption. When freeing a non-idle external buffer, we would drop it from the hash tables, then move it to the zombie list. If someone reimported the same GEM object, we would not find it in the hash tables, and go ahead and make a second iris_bo for that GEM object. But the old iris_bo would still be in the zombie list, and so we would eventually call GEM_CLOSE on it - closing a BO that should have still been live. To work around this, we defer removing a BO from the hash tables until it's actually fully closed. This has the strange effect that an external BO may be on the zombie list, and yet be resurrected before it can be properly cleaned up. In this case, we remove it from the list so it won't be freed. Fixes severe instability in Weston, which was hitting EINVALs and ENOENTs from execbuf2, due to batches referring to a GEM object that had been closed, or at least had its VMA torched. Fixes: 457a55716ea ("iris: Defer closing and freeing VMA until buffers are idle.")
* iris/bufmgr: Move iris_bo_reference into hash_find_bo, rename itKenneth Graunke2019-08-051-14/+16
| | | | | | Everybody importing an external buffer was looking it up in the hash table, then referencing it. We can just do that in the helper instead, which also gives us a convenient spot to stash extra code shortly.
* gallium: add stm DRM entry pointAhmad Fatoum2019-08-053-0/+3
| | | | | | | | | | The STM32MP157 features a Vivante GC400 GPU supported by etnaviv. Add a DRM entry point for the STM display controller, so mesa can be used with it. Signed-off-by: Ahmad Fatoum <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* lima/ppir: simplify load uni/temp op lowering and schedulingErico Nunes2019-08-042-34/+33
| | | | | | | | | | | | | | | | | | | The load uniform/temporary operations output only to a pipeline register, which must be consumed by another op in the same instruction later. The current implementation delays the decision of who will consume this result to until the scheduling step. If the consumer node is not able to use the pipeline register, a mov node may have to be created, during the scheduler step. As part of the ppir scheduler simplification, and now that the ppir scheduler supports pipeline register dependencies, this can be simplified by always creating a single mov node outputting to a normal register that can be used directly by all consumers. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: simplify select op lowering and schedulingErico Nunes2019-08-045-11/+15
| | | | | | | | | | | | | | | | | | | The select operation relies on the select condition coming from the result of the the alu scalar mult slot, in the same instruction. The current implementation creates a mov node to be the predecessor of select, and then relies on an exception during scheduling to ensure that both ops are inserted in the same instruction. Now that the ppir scheduler supports pipeline register dependencies, this can be simplified by making the mov explicitly output to the fmul pipeline register, and the scheduler can place it without an exception. Since the select condition can only be placed in the scalar mult slot, differently than a regular mov, define a separate op for it. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: support pipeline registers in schedulerErico Nunes2019-08-042-46/+65
| | | | | | | | | | | | | | | | | | | | | | | | | The ppir scheduler grew to be rather complicated and containing many exceptions as it also has to take care of inserting additional nodes when it is mandatory for nodes to be in the same instruction. As such, the lima lowering and scheduling process can be difficult to understand and maintain. The ppir lowering step created nodes hoping that the scheduler would notice the exception and do the right thing. This proposal adds a simple refactor to the scheduler so that it places nodes with pipeline registers in the same instruction. With the scheduler handling this in a general way, it is possible to create same-instruction dependencies by using pipeline registers during the lowering stage. This is simpler to maintain because now we can make these dependencies explicit in a single place (lowering), and we can drop exceptions from scheduling. Reducing the complexity of the scheduler is also useful as preparatory work to support control flow in ppir. Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Qiang Yu <[email protected]>
* lima/ppir: move alu vec to scalar lowering into NIRVasily Khoruzhick2019-08-042-107/+14
| | | | | | | | | Utgard PP is vec4, but some operations are scalar, utilize NIR vec to scalar lowering pass and indicate operations that we want to lower. Reviewed-by: Qiang Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Fix handling of SIMD32 fragment shadersJason Ekstrand2019-08-031-44/+50
| | | | | | | | | | | | | | The brw_wm_prog_data_dispatch_grf_start_reg and _prog_offset helpers read the _NPixelDispatchEnable fields from 3DSTATE_PS to figure out which bits to pull out of the prog data and stuff where. Therefore, they need to be called with the final set of _NPixelDispatchEnable bits after we've done the workaround for SIMD32 and 16x MSAA. Otherwise, if you end up with a somewhat odd combination of enables, the GRF start reg and KSP data ends up in the wrong slots. In particular, running SIMD32-only is broken but several other combinations are as well. Fixes: 5445c176e27ba "iris: Disable SIMD32 when using a 16x MSAA..." Reviewed-by: Kenneth Graunke <[email protected]>
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