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* st/va: remove TODO line for JPEG data buffer handlingLeo Liu2018-01-171-1/+0
| | | | | | | Nothing to do Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: bump glsl version to 450 for nir backendTimothy Arceri2018-01-181-6/+1
| | | | | | | | | | We still have more work to do but piglit results are looking pretty good. At GLSL 1.50 we have 30647/31118 piglit tests passing. At GLSL 4.50 we have 37927/38551 piglit tests passing. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/nir: add some missing tcs bits to the nir scan passTimothy Arceri2018-01-181-0/+14
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/radeonsi: add tcs load outputs supportTimothy Arceri2018-01-182-16/+29
| | | | | | | | | The code to load outputs is essentially the same as load inputs so we make the interface more generic to maximise code sharing. We will make use of the new support in the following patch. Reviewed-by: Nicolai Hähnle <[email protected]>
* draw: remove VSPLIT_CREATE_IDX macroRoland Scheidegger2018-01-171-11/+12
| | | | | | | Just inline the little bit of code. Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: fix vsplit code when the (post-bias) index value is -1Roland Scheidegger2018-01-172-3/+4
| | | | | | | | | | | | | | | | | | | vsplit_add_cache uses the post-bias index for hashing, but the vsplit_add_cache_uint/ushort/ubyte ones used the pre-bias index, therefore the code for handling the special case (because -1 matches the initialization value of the cache) wasn't actually working. Commit 78a997f72841310620d18daa9015633343d04db1 actually simplified the cache logic somewhat, but it looks like this particular problem carried over (and duplicated to the ushort/ubyte cases, since before only uint needed it). This could lead to the vsplit cache doing the wrong thing, in particular later fetch_info might indicate there are 0 values to fetch. This only really affected edge cases which were bogus to begin with, but it could lead to a crash with the jit vertex shader, since it cannot handle this case correctly (the count loop is always executed at least once and we would not allocate any memory for the shader outputs), so add another assert to catch it there. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/va: release held locks in error pathsGrazvydas Ignotas2018-01-173-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Found with the help of following Coccinelle semantic patch: // <smpl> @@ expression E; @@ \(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E) ... ( \(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E); ... return ...; | + maybe need_unlock(E); return ...; ) // </smpl> Signed-off-by: Grazvydas Ignotas <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
* radeon: remove unneeded semicolonsGrazvydas Ignotas2018-01-171-3/+3
| | | | | | Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom <[email protected]>
* ac: import lp_create_builder() from gallivmSamuel Pitoiset2018-01-163-42/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* st/va: clear pointers for mpeg2 quantiser matricesIndrajit Das2018-01-161-0/+5
| | | | | | | | | This is to fix VA-API issues with GStreamer and MPEG2. Since gstreamer does not pass quantiser matrices with each frame, invalid pointers were being passed to the driver. This patch addresses the same. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only update them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: update quantiser matrices only when requestedIndrajit Das2018-01-161-6/+11
| | | | | | | Only upload them when the pointers are valid. Signed-off-by: Indrajit Das <[email protected]> Reviewed-by: Christian König <[email protected]>
* Revert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"Adam Jackson2018-01-151-2/+0
| | | | | | | This reverts commit 0d044351b7043cd0bc94c1cb9b7a2213f8054414. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490 Signed-off-by: Adam Jackson <[email protected]>
* r600/shader: Initialize max_driver_temp_used correctly for the first timeGert Wollny2018-01-151-0/+1
| | | | | | | | | | | | Without this initialization the temp registers used in tgsi_declaration may used random indices, and this may result in failing translation from TGSI with an error message "GPR limit exceeded", because the random index is greater then the allowed limit implying that the shader uses more temporary registers then available. Signed-off-by: Gert Wollny <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno/ir3: "soft" depth scheduling for SFU instructionsRob Clark2018-01-141-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | First try with a "soft" depth, to try to schedule sfu instructions further from their consumers, but fall back to hard depth (which might result in stalling) if nothing else is avail to schedule. Previously the consumer of a sfu instruction could end up scheduled immediately after (since "hard" depth from sfu to consumer would be 0). This works because legalize pass would insert a (ss) sync bit, but it is sub-optimal since it would cause a stall. Instead prioritize other instructions for 4 cycles if they would no cause a nop to be inserted. This minimizes the stalling. There is a slight penalty in general to overall # of instructions in shader (since we could end up needing nop's later due to scheduling the "deeper" sfu consumer later), but ends up being a wash on register pressure. Overall this seems to be worth a 10+% gain in fps. Increasing the "soft" depth of sfu consumer beyond 4 helps a bit in some cases, but 4 seems to be a good trade-off between getting 99% of the gain and not increasing instruction count of shaders too much. It's possible a similar approach could help for tex/mem instructions, but the (sy) sync bit seems to trigger a switch to a different thread- group to hide memory latency (possibly with some limits depending on number of registers used?). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: work around SWAP vs TILE_MODE constraintRob Clark2018-01-141-0/+20
| | | | | | | | If the blit isn't changing format, but is changing tiling, just lie and call things ARGB (since the exact component order doesn't matter for a tiling blit). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: texture tilingRob Clark2018-01-1416-25/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | Overall a nice 5-10% gain for most games. And more for things like glmark2 texture benchmark. There are some rough edges. In particular, the hardware seems to only support tiling or component swap. (Ie. from hw PoV, ARGB/ABGR/RGBA/ BGRA are all the same format but with different component swap.) For tiled formats, only ARGB is possible. This isn't a big problem for *sampling* since we also have swizzle state there (and since util_format_compose_swizzles() already takes into account the component order, we didn't use COLOR_SWAP for sampling). But it is a problem if you try to render to a tiled BGRA (for example) surface. The next patch introduces a workaround for blitter, so we can generate tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render- target case. To handle that, I think we'd need to keep track that the tiled format is different from the linear format, which seems like it would get extra fun with sampler views/etc. So for now, disabled by default, enable with FD_MESA_DEBUG=ttile. In practice it works fine for all the games I've tried, but makes piglit grumpy. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-01-146-26/+35
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add screen->setup_slices() for tex layoutRob Clark2018-01-143-19/+43
| | | | | | | | The rules are sufficiently different for a5xx with tiled textures, so split this out into something that can be implemented per-generation. The a5xx specific implementation will come in a later patch. Signed-off-by: Rob Clark <[email protected]>
* r300g: remove double assignmentGrazvydas Ignotas2018-01-141-1/+0
| | | | Trivial. Found by Coccinelle.
* ac: fix build error in si_shaderMauro Rossi2018-01-131-1/+1
| | | | | | | | | | | | | | | assert() is replaced by unreachable(), to avoid following building error: external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1: error: control may reach end of non-void function [-Werror,-Wreturn-type] } ^ 1 error generated. Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi") Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radv/radeonsi/nir: lower 64bit flrpTimothy Arceri2018-01-131-0/+1
| | | | | | | | Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example: generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt2018-01-121-2/+5
| | | | | | | | I had 3.x putting swizzling in the texture state only for 16-bit texture returns, and in the shader for 32-bit. This may be due to having mixed up the return channel setup on 3.x back before I had moved it into the compiler. On 4.x, the non-border-color texwrap tests are passing nicely with both 16 and 32-bit returns with swizzling in the texture state.
* broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt2018-01-127-27/+76
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* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-121-5/+5
| | | | | Now that the actions are reused for centroid and nonperspective, give them a more generic name.
* broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt2018-01-121-2/+12
| | | | | The fxcd/fycd instructions now return half-integer pixel centers when not doing sample-rate shading.
* broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt2018-01-121-2/+4
| | | | Revealed that I was writing past the TSDA, not the Z buffer as I expected.
* broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt2018-01-127-14/+206
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* broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt2018-01-121-1/+12
| | | | | We no longer have the small depth-specific output format enum, and instead depth is just at the end of the output image format enum.
* broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt2018-01-121-3/+7
| | | | | The RGBX8 formats were dropped from V3D 4.x, but we don't really need them anyway (we already handle other non-alpha formats by forcing A to 1).
* broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt2018-01-1212-337/+451
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* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-121-3/+26
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt2018-01-129-20/+93
| | | | | This required extending the CL submit ioctl, because the tile alloc/state buffer setup has moved from the BCL to register writes.
* broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt2018-01-121-1/+1
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* broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt2018-01-129-125/+216
| | | | | | | This required moving the register accesses to a separate v3dx file, since the register definitions for each V3D version collide. It seems that initializing the v3d_hw from a file dictating 3.3 (v3d_simulator_wrapper.cpp) is safe, though.
* broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt2018-01-127-58/+360
| | | | | | | The TLB load/store path is rebuilt in this version. There is no longer a single-byte resolved store or the 3-byte extended store. Instead, you get to always use general loads/stores (which, honestly, was tempting even in previous versions).
* broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt2018-01-121-1/+1
| | | | | I accidentally emitted this into the RCL instead of the per-tile generic list, so we wouldn't get tiles after the first cleared.
* broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt2018-01-121-35/+50
| | | | | This is going to get more complicated with V3D 4.1 support, which redoes all the TLB packets.
* broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt2018-01-127-10/+24
| | | | | | To conditionally compile cl_emit() macros per V3D version, we need it to expand to whatever V3D we're building for. This required emitting #define V3D_VERSION 33 in all our currently 3.3-only code.
* meson: move libsensors dependency to libgalliumDylan Baker2018-01-118-13/+7
| | | | | | | | | This simplifies the build by removing the need to link targets against libsensors. Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Dylan Baker <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* meson: Use dependencies for nirDylan Baker2018-01-116-17/+21
| | | | | | | | | | | | | | | | | This creates two new internal dependencies, idep_nir_headers and idep_nir. The former encapsulates the generation of nir_opcodes.h and nir_builder_opcodes.h and adding src/compiler/nir as an include path. This ensures that any target that needs nir headers will have the includes and that the generated headers will be generated before the target is build. The second, idep_nir, includes the first and additionally links to libnir. This is intended to make it easier to avoid race conditions in the build when using nir, since the number of consumers for libnir and it's headers are quite high. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent style for testsDylan Baker2018-01-113-4/+12
| | | | | | | Don't use intermediate variables, use consistent whitespace. Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* meson: Use consistent styleDylan Baker2018-01-111-2/+4
| | | | | | | | | | | | | | | | | | | | Currently the meosn build has a mix of two styles: arg : [foo, ... bar], and arg : [ foo, ..., bar, ] For consistency let's pick one. I've picked the later style, which I think is more readable, and is more common in the mesa code base. v2: - fix commit message Acked-by: Eric Engestrom <[email protected]> Signed-off-by: Dylan Baker <[email protected]>
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
| | | | | | | No need for a goto. Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-111-6/+14
| | | | | | | | | | | | | Fixes the follow test for radeonsi nir: tests/spec/arb_tessellation_shader/execution/quads.shader_test Also stops 8 other tests from crashing, they now just fail e.g. tcs-output-array-float-index-rd-after-barrier.shader_test Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* tgsi: include struct definitions for tgsi_build declarationsRob Herring2018-01-101-5/+1
| | | | | | | | | | | | | | Many of the functions declared in tgsi_build.h return structs (not struct pointers). Therefore the full struct definitions are needed to avoid warnings or errors: In file included from src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:23: external/mesa3d/src/gallium/auxiliary/tgsi/tgsi_build.h:47:1: error: 'tgsi_build_header' has C-linkage specified, but returns incomplete type 'struct tgsi_header' which could be incompatible with C [-Werror,-Wreturn-type-c-linkage] This error shows up on Android builds using clang and -Werror. Cc: Ilia Mirkin <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
| | | | | | | | | | | | | | | BuilderSWR::swr_gs_llvm_fetch_input() (and consequently swr_gs_llvm_fetch_input()), did not handle the case where is_vindex_indirect or is_aindex_direct is set. Implement it, using the code in draw_llvm.c as a guideline. Fixes the following piglit tests: dynamic_input_array_index (crash) gs-input-array-vec4-index-rd vs-output-array-vec4-index-wr-before-gs Reviewed-by: Bruce Cherniak <[email protected]>
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