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* svga: change svga_destroy_shader_variant() to return voidBrian Paul2018-10-095-23/+6
* nvc0: fix blitting red to srgb8_alphaIlia Mirkin2018-10-091-0/+4
* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
* st/dri: Handle BGRA5551 formatMichel Dänzer2018-10-091-0/+13
* freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark2018-10-081-1/+1
* freedreno/a6xx: add LRZ supportRob Clark2018-10-088-132/+104
* freedreno: update generated headersRob Clark2018-10-087-38/+120
* freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark2018-10-085-38/+30
* freedreno/a6xx: remove unused fxnsRob Clark2018-10-082-19/+0
* freedreno/a6xx: remove fd6_shader_stateobjRob Clark2018-10-083-23/+10
* util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák2018-10-061-1/+3
* radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák2018-10-061-1/+1
* ac: add ac_build_roundMarek Olšák2018-10-061-3/+1
* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-064-6/+6
* ac: define all address spaces properlyMarek Olšák2018-10-061-3/+3
* gallivm: Make it possible to disable some optimization shortcuts in release b...Gert Wollny2018-10-064-21/+32
* virgl: Pass resource size and transfer offsetsTomeu Vizoso2018-10-064-28/+208
* virgl, vtest: Correct the transfer size calculationGert Wollny2018-10-061-1/+3
* radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang2018-10-054-2/+18
* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
* radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functionsMarek Olšák2018-10-051-22/+12
* radeonsi: optimizing SET_CONTEXT_REG for shaders ESSonny Jiang2018-10-055-10/+37
* virgl: Negotiate version with vtest serverTomeu Vizoso2018-10-043-0/+64
* etnaviv: Use write combine instead of unached mappings for shader boGuido Günther2018-10-041-1/+1
* freedreno: add the a6xx sources to the Android buildEmil Velikov2018-10-031-0/+1
* pipe-loader: add a dup() in pipe_loader_sw_probe_kmsEmil Velikov2018-10-032-2/+12
* pipe-loader: move dup(fd) within pipe_loader_drm_probe_fdEmil Velikov2018-10-038-44/+37
* st/nine: do not double-close the fd on teardownEmil Velikov2018-10-031-1/+1
* vl/dri3: do full teardown on screen_destroyEmil Velikov2018-10-031-1/+0
* st/dri: make swrast_no_present member of dri_screenEmil Velikov2018-10-032-4/+5
* st/dri: inline dri2_buffer.h within dri2.cEmil Velikov2018-10-034-26/+16
* st/xa: remove unused xa_screen::d[s]_depth_bits_lastEmil Velikov2018-10-031-2/+0
* r600: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
* nouveau: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
* radeonsi: use build-id when available for disk cacheTimothy Arceri2018-10-031-12/+9
* radeonsi: avoid sending GS_EMIT in shaders without outputsJózef Kucia2018-10-021-3/+6
* radeonsi: initialize ac_gpu_info::name when using SI_FORCE_FAMILYMarek Olšák2018-10-021-0/+1
* radeonsi: don't set the VS prolog key for the blit VSMarek Olšák2018-10-021-1/+2
* freedreno/a6xx: hwbinningRob Clark2018-10-028-105/+159
* freedreno: update generated headersRob Clark2018-10-027-41/+52
* radeonsi: add a workaround for bitfield_extract when count is 0Timothy Arceri2018-10-021-11/+30
* gallium/util: Clarify comment in util_init_thread_pinningMichel Dänzer2018-09-281-1/+4
* freedreno/a6xx: Build up draw dword0 outside visibilty if statementKristian H. Kristensen2018-09-271-17/+18
* freedreno/a6xx: Simplify draw_emit() branches a bitKristian H. Kristensen2018-09-271-16/+8
* freedreno/a6xx: Copy OUT_RING() part into each branch of the index ifKristian H. Kristensen2018-09-271-17/+29
* freedreno/a6xx: Split fd6_draw_emit into direct and indirect pathsKristian H. Kristensen2018-09-271-36/+46
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