| Commit message (Collapse) | Author | Age | Files | Lines |
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So that it can be hooked up pipe_context::bind_sampler_states that is
currently living on another branch.
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Fix the return type and allow src and dst types for comparison
to be separate, this at least fixes the two test cases I've written.
v2: drop the u32->s32 change
Acked-by: Christoph Bumiller <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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Reviewed-by: Christian König <[email protected]>
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When the old contents do not need to be preserved, it is faster to
create a new backing bo rather than stall.
Signed-off-by: Rob Clark <[email protected]>
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max_index may be 0xffffffff. The hardware does not need 1 + max_index
(although it does not hurt unless max_index wraps around to zero).
Signed-off-by: Rob Clark <[email protected]>
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Useful for debugging.
Signed-off-by: Rob Clark <[email protected]>
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Used by supertuxkart.
Signed-off-by: Rob Clark <[email protected]>
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For mem->gmem we don't sample depth/stencil as it's native type. So we
need to setup the swizzle state for the sampler based on the format used
for sampling.
Signed-off-by: Rob Clark <[email protected]>
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Needed by some games, like etuxracer and supertuxkart which use alpha
test rather than blending, to handle texture transparency.
Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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With a debug option to force DIRECT (mainly to make it easier for
capturing cmdstream dumps). Using INDIRECT for large shaders at least
makes a noticable reduction in CPU load, which helps for CPU limited
games.
Signed-off-by: Rob Clark <[email protected]>
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Because of how the tiling works, we can't really flush at arbitrary
points very easily. So wraparound is handled by resetting to top of
ringbuffer. Previously this would stall until current rendering is
complete. Instead cycle through multiple ringbuffers to avoid a stall.
Signed-off-by: Rob Clark <[email protected]>
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Emit markers by writing to scratch registers in order to "triangulate"
gpu lockup position from post-mortem register dump. By comparing
register values in post-mortem dump to command-stream, it is possible to
narrow down which DRAW_INDX caused the lockup.
Signed-off-by: Rob Clark <[email protected]>
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Mostly just to give an easy debug/instrumentation point.
Signed-off-by: Rob Clark <[email protected]>
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Have a single helper that all draws come through.. mainly for a
convenient debug and instrumentation point.
Signed-off-by: Rob Clark <[email protected]>
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The varying-out config comes from the inputs of the frag shader (so that
we aren't exporting unneeded varyinges). The varyings-count should come
from the frag shader as well, to avoid a discrepency in configuration
and resulting gpu lockup.
Signed-off-by: Rob Clark <[email protected]>
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Needed by glxgears and etuxracer ;-)
Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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The CP_STRMOUT_CNTL register was moved again.
Reviewed-by: Alex Deucher <[email protected]>
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start_instance doesn't affect gl_InstanceID.
There's no piglit test, but it's kinda obvious the code was wrong.
Reviewed-by: Christian König <[email protected]>
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Reviewed-by: Christian König <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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The shader is responsible for writing to streamout buffers using
the TBUFFER_STORE_FORMAT_* instructions.
The locations of some input SGPRs and VGPRs are assigned dynamically, because
the input SGPRs controlling streamout are not declared if they are not needed,
decreasing the indices of all following inputs.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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So that the "init" state is always emitted first and not later in draw_vbo.
This fixes streamout where the "init" state, which disables streamout,
was emitted in draw_vbo after streamout was enabled.
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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This could happen if set_stream_output_targets is called twice
in a row without a draw call in between.
Reviewed-by: Michel Dänzer <[email protected]>
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The register doesn't exist on SI.
Reviewed-by: Michel Dänzer <[email protected]>
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Move the code back into the common UVD files since we now
have base structures for R600 and radeonsi.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
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Fixes FTBFS on kfreebsd-*
Debian GNU/kFreeBSD doesn't provide getprogname() since it uses stdlib.h
from glibc. Instead it provides program_invocation_short_name from glibc.
You can find the same order in src/mesa/drivers/dri/common/xmlconfig.c
Cc: "9.2" <[email protected]>
Tested-by: Julien Cristau <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
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It was wrong for EXP.y, as we clamped the source before computing the
fractional part, and this opcode should be rarely used, so it's not
worth the hassle.
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- Handle more calls
- Handle more state
- Try to normalize the output a bit, to eliminate spurious differences
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Trivial.
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It is planned to ship openSUSE 13.1 with -shared libs.
nouveau.la, nv30.la, nv50.la and nvc0.la are currently LIBADDs in all nouveau
related targets.
This change makes it possible to easily build one shared libnouveau.so which is
then LIBADDed.
Also dlopen will be faster for one library instead of three and build time on
-jX will be reduced.
Whitespace fixes were requested by 'git am'.
Signed-off-by: Johannes Obermayr <[email protected]>
Acked-by: Christoph Bumiller <[email protected]>
Acked-by: Ian Romanick <[email protected]>
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Commit b77316ad7594f
st/dri: always copy new DRI front and back buffers to corresponding MSAA buffers
introduced creating a pipe_context for every call to validate, which is not required
because the callers have a context anyway.
Only exception is egl_g3d_create_pbuffer_from_client_buffer, can someone test if it
still works with NULL passed as context for validate? From examining the code I
believe it does, but I didn't thoroughly test it.
Signed-off-by: Maarten Lankhorst <[email protected]>
Cc: 9.2 <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Fixes GCC parentheses warning.
r600_texture.c: In function 'si_texture_create':
r600_texture.c:518:20: warning: suggest parentheses around arithmetic in operand of '|' [-Wparentheses]
!(templ->bind & PIPE_BIND_CURSOR | PIPE_BIND_LINEAR)) {
^
Fixes "Wrong operator used" defect reported by Coverity.
Signed-off-by: Vinson Lee <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Fixes MSVC build error introduced with commit
923d3467147dd301d94ed3e6b41295fb2bcd6f47.
src\gallium\auxiliary\util\u_cpu_detect.c(286) : fatal error C1012: unmatched parenthesis : missing '('
Signed-off-by: Vinson Lee <[email protected]>
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And update _MSC_VER comments in p_config.h
Reviewed-by: Roland Scheidegger <[email protected]>
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This is based on grepping for brw->is_haswell in i965 to see how GEN 7.5
differs from GEN 7. Slightly tested with Xonotic and some Mesa demos.
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This is now handled in the winsys.
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This aligns the gfx, compute, and dma IBs to 8 DW boundries.
This aligns the the IB to the fetch size of the CP for optimal
performance. Additionally, r6xx hardware requires at least 4
DW alignment to avoid a hw bug. This also aligns the DMA
IBs to 8 DW which is required for the DMA engine. This
alignment is already handled in the gallium driver, but that
patch can be removed now that it's done in the winsys.
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
CC: "9.2" <[email protected]>
CC: "9.1" <[email protected]>
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flags to enforce no tiling.
Signed-off-by: Axel Davy <[email protected]>
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We support indirect addressing only on the vertex index, but some
shaders also use indirect addressing on attributes. This patch
adds support for indirect addressing on both dimensions inside
gs arrays.
Signed-off-by: Zack Rusin <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: José Fonseca <[email protected]>
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Fixes warning reported by Coverity.
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