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* swr/rast: WIP builder rewrite (2)George Kyriazis2018-04-181-4/+13
* swr/rast: Add autogen of helper llvm intrinsics.George Kyriazis2018-04-1813-126/+130
* swr/rast: WIP builder rewrite.George Kyriazis2018-04-182-14/+0
* swr/rast: LLVM 6 fixGeorge Kyriazis2018-04-181-1/+1
* swr/rast: Changes to allow jitter to compile with LLVM5George Kyriazis2018-04-181-1/+17
* swr/rast: Add some archrast statsGeorge Kyriazis2018-04-189-11/+105
* swr/rast: Silence some unused variable warningsGeorge Kyriazis2018-04-181-1/+11
* swr/rast: Add debug type info for i128George Kyriazis2018-04-181-0/+1
* swr/rast: Use blend context struct to pass paramsGeorge Kyriazis2018-04-183-49/+62
* swr/rast: Introduce JIT_MEM_CLIENTGeorge Kyriazis2018-04-183-40/+71
* swr/rast: Add some instructions to jitterGeorge Kyriazis2018-04-183-0/+15
* meson: Version libMesaOpenCL like autotools doesJan Alexander Steffens (heftig)2018-04-171-2/+2
* meson: Add library versions to swr driversJan Alexander Steffens (heftig)2018-04-171-0/+4
* radeonsi: don't emit partial flushes for internal CS flushes onlyMarek Olšák2018-04-1610-20/+32
* winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATEMarek Olšák2018-04-161-10/+26
* radeonsi: implement mechanism for IBs without partial flushes at the end (v6)Marek Olšák2018-04-163-16/+47
* gallium/osmesa: link with winsock2 library on WindowsBrian Paul2018-04-131-0/+3
* gallium/util: put (void) in a few function signaturesBrian Paul2018-04-131-2/+2
* ddebug: add PIPE_OS_UNIX/LINUX checks to fix MSVC buildBrian Paul2018-04-132-2/+12
* radeonsi: restore si_emit_cache_flush call at the end of IBsMarek Olšák2018-04-131-0/+2
* gallium: move ddebug, noop, rbug, trace to auxiliary to improve build timesMarek Olšák2018-04-1378-382/+96
* radeonsi: make sure CP DMA is idle at the end of IBsMarek Olšák2018-04-133-2/+16
* gallium/hud: add a simple HUD view that only draws textMarek Olšák2018-04-132-15/+60
* radeonsi: always prefetch later shaders after the draw packetMarek Olšák2018-04-133-26/+75
* radeonsi: emit shader pointers before cache flushes & waitsMarek Olšák2018-04-131-13/+7
* radeonsi/gfx9: don't use the workaround for gather4 + stencilMarek Olšák2018-04-131-2/+11
* radeonsi: disable TC-compat HTILE on Tonga and IcelandMarek Olšák2018-04-131-0/+7
* radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabledMarek Olšák2018-04-131-9/+7
* radeonsi: don't flush HTILE if there is no HTILE clearMarek Olšák2018-04-131-2/+2
* radeonsi: merge 2 identical if statements in si_clearMarek Olšák2018-04-131-9/+2
* radeonsi: don't do GFX-specific texture decompression for computeMarek Olšák2018-04-131-10/+10
* radeonsi: simplify generating the renderer stringMarek Olšák2018-04-131-11/+8
* Fix scons buildMarek Olšák2018-04-124-1/+10
* mesa: include mtypes.h lessMarek Olšák2018-04-122-2/+1
* broadcom/vc5: Fix a stray '`' in a comment.Eric Anholt2018-04-121-1/+1
* broadcom/vc5: Update the UABI for in/out syncobjsEric Anholt2018-04-129-90/+55
* broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2018-04-122-11/+0
* broadcom/vc5: Drop the throttling code.Eric Anholt2018-04-121-9/+0
* broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt2018-04-121-28/+29
* broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt2018-04-121-13/+13
* broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt2018-04-121-23/+13
* broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt2018-04-121-5/+16
* broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt2018-04-121-0/+8
* broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt2018-04-121-2/+4
* st/va: add VP9 config to enable profile2Leo Liu2018-04-122-1/+5
* radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu2018-04-121-1/+2
* radeon/vcn: add VP9 profile2 supportLeo Liu2018-04-121-0/+16
* vl: add VP9 profile2 supportLeo Liu2018-04-122-1/+3
* st/va: add VP9 config to enable profile0Leo Liu2018-04-122-1/+5
* st/va: parse VP9 uncompressed frame headerLeo Liu2018-04-123-1/+239
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