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* st/glsl_to_tgsi: provide Texture and Format information for image opsNicolai Hähnle2016-03-142-5/+15
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add Texture and Format to tgsi_instruction_memoryNicolai Hähnle2016-03-142-1/+11
| | | | | | | | Frontends should have this information readily available, and it simplifies image LOAD/STORE/ATOM* handling especially with indirect image access. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* clover: Fix pipe_grid_info.indirect not being initialized.Hans de Goede2016-03-141-1/+1
| | | | | | | | | | | | | | After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass uninitialized memory for it to launch_grid. This commit fixes this by zero-ing the entire pipe_grid_info struct when declaring it, to avoid similar problems popping-up in the future. Cc: "11.2" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> [ Francisco Jerez: Trivial codestyle fix. ] Reviewed-by: Francisco Jerez <[email protected]>
* gallium/swr: Resource managementBruce Cherniak2016-03-1410-143/+265
| | | | | | | | Better tracking of resource state and synchronization. A follow on commit will clean up resource functions into a new swr_resource.cpp file. Reviewed-By: George Kyriazis <[email protected]>
* nv50,nvc0: Set only NEW_CP_GLOBALS upon bindingPierre Moreau2016-03-132-2/+2
| | | | | Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* freedreno/ir3: lower extract_byte/wordRob Clark2016-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | The following commits broke things by starting to feed us unhandled extract_u16/extract_u8 opcodes: commit 905ff861982450831a56d112036f68a751337441 Author: Matt Turner <[email protected]> AuthorDate: Wed Feb 3 14:28:31 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u16. commit 76289fbfa84a06ef4db8ad44ea0eb88ad0be8d5c Author: Matt Turner <[email protected]> AuthorDate: Thu Jan 21 09:09:48 2016 -0800 Commit: Matt Turner <[email protected]> CommitDate: Fri Mar 4 11:52:34 2016 -0800 nir: Recognize open-coded extract_u8. Signed-off-by: Rob Clark <[email protected]>
* nv50,nvc0: handle SQRT lowering inside the driverIlia Mirkin2016-03-136-23/+27
| | | | | | | | | | | | | | | | | | | | | First off, st/mesa lowers DSQRT incorrectly (it uses CMP to attempt to find out whether the input is less than 0). Secondly the current approach (x * rsq(x)) behaves poorly for x = inf - a NaN is produced instead of inf. Instead we switch to the less accurate rcp(rsq(x)) method - this behaves nicely for all valid inputs. We still don't do this for DSQRT since the RSQ/RCP ops are *really* inaccurate, and don't even have Newton-Raphson steps right now. Eventually we should have a separate library function for DSQRT that does it more precisely (and perhaps move this lowering to the post-opt phase). This fixes a number of dEQP precision tests that were expecting better behavior for infinite inputs. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Samuel Pitoiset <[email protected]>
* nv50/ir: avoid folding mul + add if the mul has a dnzIlia Mirkin2016-03-131-3/+2
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nvc0: fix blit triangle size to fully cover FB's > 8192x8192Ilia Mirkin2016-03-131-4/+4
| | | | | | | | | | | | | | The idea is that a single triangle will cover the whole area being drawn, allowing the blit shader to do its work. However the max fb size is 16384x16384, which means that the triangle we draw needs to be twice that in order to cover the whole area fully. Increase the size of the triangle to 32768x32768. This fixes a number of dEQP tests that were failing because a blit was involved which would miss some of the resulting texture. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* freedreno: OUT_RELOC vs OUT_RELOCW fixesRob Clark2016-03-133-7/+7
| | | | | | Make sure we use OUT_RELOCW() in cases where the buffer is written to. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: hw binningRob Clark2016-03-134-33/+210
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: use generated headers for draw initiatorRob Clark2016-03-131-3/+4
| | | | | | No need to open-code this. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: remove RB_RENDER_CONTROL patchingRob Clark2016-03-136-41/+8
| | | | | | | | | Bitfields where shuffled around for the better on a4xx, so we don't need any patching on this one. It appears to be something we set entirely in the gmem code so no conflict between tiling and render state like we had in a3xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2016-03-135-11/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
| | | | | | | Move where we pick dummy FS for binning pass, so the whole driver sees the same dummy/no-op FS stage. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: constify the shader variantsRob Clark2016-03-132-6/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: constify the shader variantsRob Clark2016-03-134-13/+13
| | | | | | Most of the driver just needs read-only access, so constify.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: remove duplicate mark of end of binning cmdsRob Clark2016-03-131-3/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: avoid crash when a sampler state is bound for a buffer textureNicolai Hähnle2016-03-131-0/+1
| | | | | | | | | | | | | Sampler states don't really make sense with buffer textures, but they can be set anyway, so we need to be defensive here. This bug was lurking for a while and was finally noticed due to PBO uploads setting sampler states. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94284 Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Laurent Carlier <[email protected]> Tested-by: Shawn Starr <[email protected]>
* st/va: add HEVC main 10 profileBoyuan Zhang2016-03-111-1/+4
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/video: enable HEVC main 10 decodeBoyuan Zhang2016-03-111-2/+6
| | | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-112-5/+8
| | | | | | | | | | Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. v3: Check that we have a real texture (Nicolai) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: clear compressed_depthtex/colortex_mask when binding buffer textureNicolai Hähnle2016-03-111-12/+12
| | | | | | | | | | | Found by inspection of the source based on a bisected bug report. This bug has been in the code for a long time, but the more recent PBO upload feature exposed it because it leads to more uses of buffer textures. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94388 Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0 11.1 11.2" <[email protected]>
* nvc0: add support for TGSI FMA opsIlia Mirkin2016-03-102-1/+7
| | | | | | | | This will allow the nouveau backend to not try and split up ops that are fused in GLSL. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-103-2/+51
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move si_decompress_textures to si_blit.cNicolai Hähnle2016-03-103-23/+23
| | | | | | | | | Since it is all about calling into blitter functions, it makes more sense here. This change also reduces the size of the interfaces between .c files. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-101-0/+30
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: notify all contexts when cmasks are enabled/disabledNicolai Hähnle2016-03-102-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is an annoying corner case that I stumbled across while looking into piglit's arb_shader_image_load_store/execution/load-from-cleared-image.shader_test (which can be easily adapted to demonstrate the bug without the ARB_shader_image_load_store extension) When we bind a texture and then clear it using glClear (by attaching it to the current framebuffer) for the first time, we allocate a separate cmask for the texture to do fast clear, but the corresponding bit in compressed_colortex_mask is not set. Subsequent rendering will use incorrect data. Conversely, when a currently bound texture with an existing cmask is exported leading to that cmask being disabled, the compressed_colortex_mask bit will remain set, leading to an assertion later on in debug builds. Since iterating through all contexts and/or remembering where every texture is bound would be costly, and cmask enable/disable should be rare, we will maintain a global counter to signal contexts that they must update their compressed_colortex_masks. This patch introduces the global counter, and subsequent patches will do the mask update. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/swr: remove use of BYTE from swr driverTim Rowley2016-03-104-14/+14
| | | | | | Remove use of a win32-style type leaked from the swr rasterizer. Reviewed-by: Bruce Cherniak <[email protected]>
* nvc0: expose SM35 perf counters to AMD_performance_monitorSamuel Pitoiset2016-03-101-2/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add driver metrics for SM35 (GK110)Samuel Pitoiset2016-03-101-1/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: add MP performance counters for SM35 (GK110)Samuel Pitoiset2016-03-103-17/+204
| | | | | | | | | Because compute support is not enabled by default for these chipsets, NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable performance counters. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: explode config of Kepler hardware SM eventsSamuel Pitoiset2016-03-101-78/+477
| | | | | | | | This is really verbose but most of the configuration will be reused for SM35 (GK110). Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: rework the driver metrics infrastructureSamuel Pitoiset2016-03-103-157/+172
| | | | | | | This follows the same design as MP perf counters. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nvc0: rework the MP counters infrastructureSamuel Pitoiset2016-03-104-268/+243
| | | | | | | This mainly improves how we define the different list of queries. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* nouveau: Fix clang reserved-user-defined-literal error.Vinson Lee2016-03-091-1/+1
| | | | | | | | | | | | CXX codegen/nv50_ir.lo In file included from codegen/nv50_ir.cpp:28: ./nouveau_debug.h:19:30: error: invalid suffix on literal; C++11 requires a space between literal and identifier [-Wreserved-user-defined-literal] fprintf(stderr, "%s:%d - "fmt, __FUNCTION__, __LINE__, ##args) ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: use explicit drm_major, drm_minor checkEmil Velikov2016-03-091-1/+2
| | | | | | | | | | Just like everywhere else in the radeon codebase. v2: Don't forget about drm_major == 3 (Alex) Cc: Alex Deucher <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: do not wrap header inclusion inEmil Velikov2016-03-099-19/+28
| | | | | | | | | | | | | | | | Add one missing extern C guard within include/pipe/p_video_enums.h, and remove the wrapping throughout gallium. On Haiku one could even use the gallium debug_printf() although that's another topic. v2: Leave dbghelp.h as is (Jose) Cc: Jose Fonseca <[email protected]> Cc: Brian Paul <[email protected]> Cc: Alexander von Gluck IV <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* winsys/amdgpu/addrlib: do not wrap header inclusion in extern "C"Emil Velikov2016-03-091-2/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallivm: special case TGSI_OPCODE_STORENicolai Hähnle2016-03-091-1/+1
| | | | | | | | This instruction has the resource (buffer or image) as a destination to represent the writemask for SSBO writes. However, this is obviously not a "real" destination for the purpose of emitting LLVM IR. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: set correct output mode for RESQNicolai Hähnle2016-03-091-1/+1
| | | | | Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add CAPs returning PCI device locationMarek Olšák2016-03-0916-0/+76
| | | | Reviewed-by: Brian Paul <[email protected]>
* winsys/amdgpu: get PCI infoMarek Olšák2016-03-092-2/+21
| | | | | | | | | This will be queried by the OpenCL stack using an interop call. I have tested that the values match lspci. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set amdgpu metadata before exporting a textureMarek Olšák2016-03-096-2/+78
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: extract the texture descriptor computation into its own functionNicolai Hähnle2016-03-091-164/+186
| | | | | | | This will allow this code to be re-used for shader images. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: extract the buffer descriptor computation into its own functionNicolai Hähnle2016-03-091-25/+48
| | | | | | | This will allow it to be re-used for shader image descriptors. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: remove resource field from si_sampler_viewNicolai Hähnle2016-03-093-4/+2
| | | | | | | view->resource is redundant with view->base.texture, so get rid of it. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: accept pipe_resource in si_sampler_view_add_bufferMarek Olšák2016-03-091-11/+12
| | | | | | | | | | and rename .._buffers -> .._buffer Based loosely on Nicolai's patch. This will make it easier to cherry-pick Nicolai's patches from his image support branch. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
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