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* nvc0: store the number of GPCs to nvc0_screenSamuel Pitoiset2015-10-162-0/+2
* nvc0: fix unaligned mem access when reading MP counters on FermiSamuel Pitoiset2015-10-161-6/+12
* nvc0: fix monitoring multiple MP counters queries on FermiSamuel Pitoiset2015-10-161-76/+87
* nvc0: fix queries which use multiple MP counters on FermiSamuel Pitoiset2015-10-161-47/+81
* nvc0: allow to use 8 MP counters on FermiSamuel Pitoiset2015-10-162-19/+13
* nvc0: fix sequence field init for MP counters on FermiSamuel Pitoiset2015-10-161-2/+4
* nvc0: correctly enable the MP counters' multiplexer on FermiSamuel Pitoiset2015-10-161-4/+1
* nvc0: rip off the kepler MP-enabling logic from the Fermi codepathSamuel Pitoiset2015-10-161-7/+1
* nvc0: split out begin_query() hook used by MP countersSamuel Pitoiset2015-10-161-24/+84
* nvc0: remove useless call to query_get_cfg() in nvc0_hw_sm_query_end()Samuel Pitoiset2015-10-161-3/+1
* svga: only count hardware buffer mappings for HUDBrian Paul2015-10-162-1/+3
* svga: add new GALLIUM_HUD queriesNeha Bhende2015-10-1616-38/+196
* svga: use new svga_new_shader_variant() functionBrian Paul2015-10-164-2/+12
* svga: pass context to svga_tgsi_vgpu9_translate()Brian Paul2015-10-164-4/+8
* svga: remove svga_tgsi_vgpu9_translate() call in GS pathBrian Paul2015-10-161-7/+3
* freedreno: add debug option to dirty state after drawRob Clark2015-10-153-2/+7
* freedreno/a3xx: cache-flush is needed after MEM_WRITERob Clark2015-10-153-5/+14
* gallium/util: fix debug_get_flags_option on 32-bit harderRob Clark2015-10-151-3/+3
* nv30: include the header of ffs prototypeChih-Wei Huang2015-10-151-0/+1
* nv50/ir: use C++11 standard std::unordered_map if possibleChih-Wei Huang2015-10-151-3/+17
* r600/vce: enable VCE for trinity/richlandChristian König2015-10-131-1/+21
* r600/uvd: disable UVD tiling by defaultChristian König2015-10-131-3/+5
* r600g: Enable GL_ARB_gpu_shader5 extensionGlenn Kennard2015-10-131-1/+1
* r600g/sb: SB support for UBO indexingGlenn Kennard2015-10-1311-27/+140
* r600g/sb: Support gs5 sampler indexing (v2)Glenn Kennard2015-10-139-25/+195
* nouveau: avoid double-emitting fenceIlia Mirkin2015-10-121-1/+5
* u_vbuf: fix vb slot assignment for translated buffersNicolai Hähnle2015-10-121-0/+1
* ilo: improve Gen8 defines based on its PRMsChia-I Wu2015-10-1213-121/+399
* nv50,nvc0: don't base decisions on available pushbuf spaceIlia Mirkin2015-10-113-35/+10
* nouveau: avoid emitting new fences unnecessarilyIlia Mirkin2015-10-111-3/+9
* nvc0: make use of NVC0_COMPUTE_CLASS for GF110Samuel Pitoiset2015-10-101-5/+2
* tgsi: (trivial) kill c99-ism.Roland Scheidegger2015-10-091-2/+3
* tgsi/scan: add info about declared samplers (v2)Marek Olšák2015-10-092-0/+3
* tgsi: add a utility for emulating some GL featuresMarek Olšák2015-10-093-0/+208
* glsl: move shader_enums into nirRob Clark2015-10-094-3/+3
* nvc0: move HW SM queries to nvc0_query_hw_sm.c/h filesSamuel Pitoiset2015-10-098-796/+908
* nvc0: move HW queries to nvc0_query_hw.c/h filesSamuel Pitoiset2015-10-098-1215/+1310
* nvc0: move SW queries to nvc0_query_sw.c/h filesSamuel Pitoiset2015-10-095-84/+204
* nvc0: move nvc0_so_target_save_offset() to its correct locationSamuel Pitoiset2015-10-093-24/+19
* nvc0: add a header file for nvc0_querySamuel Pitoiset2015-10-097-189/+202
* gallium/ddebug: add missing dd_util.h to sources listEmil Velikov2015-10-081-1/+2
* gallium/ddebug: automake: sort sources alphabeticallyEmil Velikov2015-10-081-2/+2
* radeonsi: fix a GS hang on VIMarek Olšák2015-10-072-0/+19
* radeonsi: remove TC L2 cache flush for index buffers on VIMarek Olšák2015-10-071-3/+3
* svga: whitespace fixes in svga_sampler_view.cBrian Paul2015-10-071-8/+16
* svga: whitespace fixes in svga_resource_buffer.cBrian Paul2015-10-071-26/+27
* svga: round UBO constant buffer size up/down to multiple of 16 bytesBrian Paul2015-10-071-0/+18
* nouveau: make sure there's always room to emit a fenceIlia Mirkin2015-10-074-2/+8
* vc4: use nir two-sided-color loweringBoyan Ding2015-10-062-24/+2
* vc4: Fix a leak of the last color read/write surface on context destroy.Eric Anholt2015-10-061-0/+3
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