summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Expand)AuthorAgeFilesLines
...
* a2xx: add support for a few 16-bit color rendering formatsIlia Mirkin2017-10-152-1/+11
* freedreno/a20x: Enable rendering to RGBA/RGBXWladimir J. van der Laan2017-10-151-1/+3
* freedreno/a20x: Fix rendering to BGRXWladimir J. van der Laan2017-10-151-0/+1
* etnaviv: rework TS enable to be a derived stateLucas Stach2017-10-143-5/+43
* etnaviv: skip unused vertex attributes when assigning VS inputsLucas Stach2017-10-141-0/+4
* st/dri: Add definitions to allow importing 16-bit surfacesMark Thompson2017-10-131-0/+14
* broadcom/vc5: Remove the u_resource_vtbl usage.Eric Anholt2017-10-123-25/+18
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-122-2/+79
* winsys/amdgpu: implement sync_file import/exportMarek Olšák2017-10-123-7/+138
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-121-0/+1
* st/dri: implement __DRIimageExtension::validateUsage properlyMarek Olšák2017-10-121-8/+22
* gallium: add pipe_screen::check_resource_capabilityMarek Olšák2017-10-125-0/+74
* etnaviv: Do GC3000 resolve-in-place when possibleWladimir J. van der Laan2017-10-124-4/+25
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
* gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formatsNicolai Hähnle2017-10-121-0/+13
* swr: simd16 shaders work in progressTim Rowley2017-10-113-2/+21
* gallium: allow 512-bit vectorsTim Rowley2017-10-112-9/+9
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
* Android: fix build break from r600/radeon splitRob Herring2017-10-103-2/+6
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-101-4/+25
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-101-0/+4
* broadcom/vc5: Fix color masks for non-independent blending.Eric Anholt2017-10-101-8/+16
* broadcom/vc5: Make the BCL's number of render targets setup match the RCL.Eric Anholt2017-10-101-1/+2
* braodcom/vc5: Fix tile size setup for MRTs.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-101-3/+9
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-102-1/+4
* braodcom/vc5: Find the actual first TF output for our TF spec.Eric Anholt2017-10-101-1/+6
* broadcom/vc5: Fix translation of transform feedback's output_register field.Eric Anholt2017-10-101-2/+16
* broadcom/vc5: Mark our primitives as needing TF processing.Eric Anholt2017-10-101-4/+11
* broadcom/vc5: Fix setup of TF dword output count.Eric Anholt2017-10-101-1/+1
* broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup.Eric Anholt2017-10-101-1/+3
* broadcom/vc5: Flush the job when mapping a transform feedback buffer.Eric Anholt2017-10-103-0/+32
* broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.Eric Anholt2017-10-102-3/+3
* broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Fix depth and stencil clear values.Eric Anholt2017-10-103-14/+10
* broadcom/vc5: Add missing Z16 format.Eric Anholt2017-10-101-0/+1
* braodcom/vc5: Fix incorrect early Z writes in discard shaders.Eric Anholt2017-10-101-1/+6
* broadcom/vc5: Add proper support for base_vertex and base_instance.Eric Anholt2017-10-103-20/+24
* broadcom/vc5: Use supertiles and generic tile lists.Eric Anholt2017-10-103-73/+130
* broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.Eric Anholt2017-10-1042-2/+9129
* nir: Move vc4's alpha test lowering to core NIR.Eric Anholt2017-10-103-55/+11
* broadcom/vc4: Expose PIPE_CAP_TILE_RASTER_ORDEREric Anholt2017-10-107-20/+71
* gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt2017-10-1018-0/+29