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* radeonsi: inline txq_fetch_argsMarek Olšák2018-08-141-26/+7
* radeonsi: use get_resinfo directly in lower_gather4_integerMarek Olšák2018-08-141-13/+12
* radeonsi: inline tex_fetch_args into build_tex_intrinsicMarek Olšák2018-08-141-222/+188
* radeonsi: remove fetch_args callbacks for ALU instructionsMarek Olšák2018-08-142-103/+55
* radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.cMarek Olšák2018-08-148-319/+348
* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-147-2/+95
* gallium/u_blitter: save/restore window rectanglesMarek Olšák2018-08-142-0/+29
* noop: implement set_window_rectanglesMarek Olšák2018-08-141-0/+8
* ddebug: implement set_window_rectanglesMarek Olšák2018-08-141-0/+12
* freedreno/ir3: add support for a6xx 'merged' register setRob Clark2018-08-142-2/+24
* freedreno/ir3: small RA cleanupRob Clark2018-08-142-13/+8
* freedreno/ir3: stop hard-coding FS input regsRob Clark2018-08-147-183/+103
* freedreno/ir3: use r63.x for unused inputsRob Clark2018-08-141-3/+3
* freedreno/ir3: create all inputs in first blockRob Clark2018-08-141-17/+17
* freedreno/ir3: rename s/frag_pos/frag_vcoord/gRob Clark2018-08-142-17/+22
* freedreno/ir3: move per-generation compiler configRob Clark2018-08-143-43/+52
* freedreno: move free() into fdN_context_destroy()Rob Clark2018-08-145-2/+7
* freedreno: a2xx: ir2 updateJonathan Marek2018-08-145-545/+615
* virgl: ARB_texture_barrier supportDave Airlie2018-08-146-3/+24
* Gallium/tgsi: Correct signdness of return value of bit operationsGert Wollny2018-08-111-3/+4
* meson: Build with Python 3Mathieu Bridon2018-08-107-15/+15
* python: Fix inequality comparisonsMathieu Bridon2018-08-101-0/+6
* python: Better check for integer typesMathieu Bridon2018-08-091-2/+11
* vc4: Implement texture_subdata() to directly upload tiled data.Eric Anholt2018-08-081-1/+39
* vc4: Handle partial loads/stores of tiled textures.Eric Anholt2018-08-083-60/+155
* vc4: Compile the LT image helper per cpp we might load/store.Eric Anholt2018-08-081-2/+31
* vc4: Refactor to reuse the LT tile walking code.Eric Anholt2018-08-081-24/+34
* svga: use pipe_sampler_view::target in svga_set_sampler_views()Brian Paul2018-08-081-1/+1
* svga: use SVGA3D_RS_FILLMODE for vgpu9Brian Paul2018-08-083-26/+37
* svga: add TGSI_SEMANTIC_FACE switch case in svga_swtnl_update_vdecl()Brian Paul2018-08-081-0/+1
* ttn: remove {varying_slot, frag_result}_to_tgsi_semantic helpersEmil Velikov2018-08-082-79/+0
* vc4: Fix vc4_fence_server_sync() on pre-syncobj kernels.Eric Anholt2018-08-071-1/+2
* vc4: Ignore samplers for finding uniform offsets.Eric Anholt2018-08-071-3/+14
* vc4: Extend dumping of uniforms in QIR and in the command stream.Eric Anholt2018-08-073-13/+68
* vc4: Pull uinfo->data[i] dereference out to the top of the loop.Eric Anholt2018-08-071-20/+18
* vc4: Make sure to emit a tile coordinates between two MSAA loads.Eric Anholt2018-08-071-12/+11
* vc4: Respect a sampler view's first_layer field.Eric Anholt2018-08-071-1/+3
* virgl: add ARB_shader_clock supportDave Airlie2018-08-082-1/+3
* python: Use explicit integer divisionsMathieu Bridon2018-08-072-4/+7
* dri: Add param driCreateConfigs(mutable_render_buffer)Chad Versace2018-08-071-2/+2
* radeonsi: set GLC=1 for all write-only shader resourcesMarek Olšák2018-08-071-2/+19
* radeonsi: don't load block dimensions into SGPRs if they are not variableMarek Olšák2018-08-073-7/+7
* swr: don't export swr_create_screen_internalEmil Velikov2018-08-072-2/+1
* virgl: update virgl_hw.h from virglrendererErik Faye-Lund2018-08-071-1/+26
* virgl: rename msaa_sample_positions -> sample_locationsErik Faye-Lund2018-08-072-5/+5
* vc4: Fix a leak of the no-vertex-elements workaround BO.Eric Anholt2018-08-061-0/+2
* vc4: Fix context creation when syncobjs aren't supported.Eric Anholt2018-08-061-2/+6
* v3d: Emit the VCM_CACHE_SIZE packet.Eric Anholt2018-08-062-0/+9
* v3d: Drop "VC5" from the renderer string.Eric Anholt2018-08-061-1/+1
* drisw: Fix build on Android Nougat, which lacks shm (v2)Chad Versace2018-08-061-0/+11
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