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* gallium/radeon: update documentation of buffer_get_virtual_addressNicolai Hähnle2016-09-301-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: emit relocations for query fencesNicolai Hähnle2016-09-304-9/+15
| | | | | | | | | This is only needed for r600 which doesn't have ARB_query_buffer_object and therefore wouldn't really need the fences, but let's be optimistic about filling in this feature gap eventually. Cc: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/uvd: adjust the buffer offset when relocation is usedNicolai Hähnle2016-09-301-0/+1
| | | | | | | We don't plan to use sub-allocated buffers with UVD, but just in case one slips through, this increases the chances of things working out anyway. Reviewed-by: Christian König <[email protected]>
* radeon/vce: adjust the buffer offset when relocation is usedNicolai Hähnle2016-09-301-0/+1
| | | | | | | We don't plan to use sub-allocated buffers with VCE, but just in case one slips through, this increases the chances of things working out anyway. Reviewed-by: Christian König <[email protected]>
* radeon/video: don't use sub-allocated buffersNicolai Hähnle2016-09-302-1/+10
| | | | | | | Cc: Christian König <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969 Reviewed-by: Christian König <[email protected]>
* gallium/hud: Add power sensor supportSteven Toth2016-09-294-5/+45
| | | | | | | | | | | | | Implement support for power based sensors, reporting units in milli-watts and watts. Also, minor cleanup - change the related if block to a switch. Tested with two different power sensors, including the nouveau 'power1' sensors on a GTX950 card. Signed-off-by: Steven Toth <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv50/ir: teach insnCanLoad() about SHLADDSamuel Pitoiset2016-09-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Commutativity is not allowed with SHLADD, but src2 can accept loads. To allow the load propagation pass to do its job, add a special case like for SUCLAMP because src1 is always an immediate. This IMAD to SHLADD optimization helps a bunch of shaders from Tomb Raider, Victor Vran, UE4 demos (+15% perf with Elemental) and Shadow Warrior. GF100/GK104: total instructions in shared programs :2838045 -> 2834712 (-0.12%) total gprs used in shared programs :396684 -> 396386 (-0.08%) total local used in shared programs :34416 -> 34416 (0.00%) local gpr inst bytes helped 0 326 1105 1105 hurt 0 55 3 3 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)Samuel Pitoiset2016-09-291-0/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)Samuel Pitoiset2016-09-291-0/+8
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: optimize IMAD to SHLADD in presence of power of 2Samuel Pitoiset2016-09-291-0/+7
| | | | | | | Only and only if src1 is a power of 2 we can replace IMAD by SHLADD. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add emission for SHLADDSamuel Pitoiset2016-09-293-0/+127
| | | | | | | | Unfortunately, we can't use the emit helpers for GF100/GK110 because src1 and src2 are swapped. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: add preliminary support for SHLADDSamuel Pitoiset2016-09-295-7/+17
| | | | | | | | | | This instruction is available since SM20 (Fermi) and allow to do (a << b) + c in one shot. In some situations, IMAD should be replaced by SHLADD when b is a power of 2, and ADD+SHL should be replaced by SHLADD as well. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: update GM107 sched control codes formatSamuel Pitoiset2016-09-292-23/+23
| | | | | | | | | envyas now uses a much better representation for those control codes and it displays the different flags instead of an unreadable hex number. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: use smaller buffers for query resultsNicolai Hähnle2016-09-291-1/+1
| | | | | | | Most of the time, even the 512 bytes that we now get is more than sufficient (pipeline stats queries are the largest at 184 bytes per shot). Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon/winsyses: add radeon_winsys::min_alloc_sizeNicolai Hähnle2016-09-293-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable ARB_query_buffer_object (v2)Nicolai Hähnle2016-09-291-7/+14
| | | | | | | v2: enable only when compute is available Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: implement get_query_result_resource (v2)Nicolai Hähnle2016-09-294-1/+402
| | | | | | | v2: fix a comment (Gustaw Smolarczyk) Acked-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: zero all query buffersNicolai Hähnle2016-09-292-17/+11
| | | | | | | To ensure that fences are properly initialized. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: cleanup getting PIPE_QUERY_TIMESTAMP resultNicolai Hähnle2016-09-291-5/+1
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add query fences and r600_get_hw_query_paramsNicolai Hähnle2016-09-291-16/+91
| | | | | | | | | | | | | | | | | We will support the waiting option in ARB_query_buffer_object using WAIT_REG_MEM on an appropriate fence-like dword. Some queries conveniently write their results with the highest bit set, and we can just use that; for others, we have to write a fence explicitly. ZPASS_DONE for occlusion queries writes its results with the high bit set, but it writes up to 8 pairs of results (one for each DB). We have to wait for all of these results, so let's just add an explicit fence. The new function provides summary information to be used by subsequent patches. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add save_qbo_stateNicolai Hähnle2016-09-293-0/+22
| | | | | | | | Save compute shader state that will be used for the ARB_query_buffer_object implementation. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)Nicolai Hähnle2016-09-292-0/+51
| | | | | | | | | | These functions extract the pipe state structure from the current descriptors, for state saving. v2: correctly dereference *buf (Bas) Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add r600_gfx_{write,wait}_fenceNicolai Hähnle2016-09-293-38/+60
| | | | | | | For bottom-of-pipe fences inside the gfx command stream. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add barrier_flags to r600_common_screenNicolai Hähnle2016-09-293-0/+23
| | | | | | | | | | | There are driver-specific context flags for barriers that are not covered by the Gallium barrier interfaces. The R600 settings of these flags may not be optimal, but we're not going to use them yet anyway. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: Add support for block I/O, network I/O and lmsensor statsSteven Toth2016-09-288-0/+1264
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V8: Feedback based on peer review convert if block into a switch Constify some func args V7: Increase precision when measuring lmsensors volts Flatten patch series. V6: Feedback based on peer review Simplify sensor initialization (arg passing). Constify some func args V5: Feedback based on peer review Convert sprintf to snprintf Convert char * to const char * int arg converted to bool Func changes to take a filename vs a larger struct. Omit the space between '*' and the param name. V4: Merged with master as of 2016/9/27 6pm V3: Flatten the entire patchset ready for the ML V2: Additional seperate patches based on feedback a) configure.ac: Add a comment related to libsensors b) HUD: Disable Block/NIC I/O stats by default. Implement configuration option --enable-gallium-extra-hud=yes and enable both statistics when this option is enabled. c) Configure.ac: Minor cleanup to user visible configuration settings d) Configure.ac: HUD stats - build system improvements Move the -lsensors out of a deeper Makefile, bring it into the configure.ac. Also, rename a compiler directive to more closely follow the standard. V1: Initial release to the ML Three new features: 1. Disk/block I/O device read/write stats MB/ps. 2. Network Interface RX/TX transfer statistics as a percentage of the overall NIC speed. 3. lmsensor power, voltage and temperature sensors. The lmsensor changes makes a dependency on libsensors so support for the change is opt out by default. Signed-off-by: Steven Toth <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* vc4: Emit perf debug when we fall back to quad clears.Eric Anholt2016-09-281-0/+2
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* gallium/radeon: Initialize pipe_resource::next to NULLMichel Dänzer2016-09-282-0/+2
| | | | | | | Fixes lots of piglit tests crashing due to using uninitialized memory. Fixes: ecd6fce2611e ("mesa/st: support lowering multi-planar YUV") Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* swr: replace gallium->swr format enum conversionTim Rowley2016-09-271-51/+293
| | | | | | Replace old string comparison with a mapping table. Reviewed-by: Bruce Cherniak <[email protected]>
* gallium/radeon/winsyses: reduce the number of pb_cache bucketsNicolai Hähnle2016-09-273-9/+5
| | | | | | | Small buffers are now handled via the slabs code, so separate buckets in pb_cache have become redundant. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: enable buffer allocation from slabsNicolai Hähnle2016-09-274-2/+209
| | | | | | | Only enable for chips with GPUVM, because older driver paths do not take the required offset into account. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add fine-grained fences for slab buffersNicolai Hähnle2016-09-275-11/+137
| | | | | | | | | | | | | | | Note the logic for adding fences is somewhat different than for amdgpu, because radeon has no scheduler and we therefore have no guarantee about the order in which submissions from multiple threads are processed. (Ironically, this is only an issue when "multi-threaded submission" is disabled, because "multi-threaded submission" actually means that all submissions happen from a single thread that happens to be separate from the application's threads. If we only supported "multi-threaded submission", the fence handling could be simplified by adding the fences in that thread where everything is serialized.) Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add slab buffer listNicolai Hähnle2016-09-275-12/+107
| | | | | | | Introducing radeon_bo::hash will reduce collisions between "real" buffers and buffers from slabs. Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: separate adding a buffer from updating its reloc dataNicolai Hähnle2016-09-271-35/+17
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/radeon: add slab entry structures to radeon_boNicolai Hähnle2016-09-272-39/+78
| | | | | | Already adjust the map/unmap logic accordingly. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: enable buffer allocation from slabsNicolai Hähnle2016-09-274-0/+201
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add fence and buffer list logic for slab allocated buffersNicolai Hähnle2016-09-273-45/+152
| | | | Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add slab entry structures to amdgpu_winsys_boNicolai Hähnle2016-09-273-36/+74
| | | | | | Already adjust amdgpu_bo_map/unmap accordingly. Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: do not synchronize unsynchronized buffersNicolai Hähnle2016-09-273-45/+118
| | | | | | | | | | | | | | | | | | | | When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now no longer add a dependency on the buffer's fence(s). However, we still need to add a fence to the buffer during flush, so that cache reclaim works correctly (and in the hypothetical case that the buffer is later added to a CS _with_ the SYNCHRONIZED flag). It is now possible that the submissions refererring to a buffer are no longer linearly ordered, and so we may have to keep multiple fences around. We keep the fences in a FIFO. It should usually stay quite short (# of contexts * 2, for gfx + dma rings). While we're at it, extract amdgpu_add_fence_dependency for a single buffer, which will make adding the distinction between real buffer and slab cases easier. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add RADEON_FLAG_HANDLENicolai Hähnle2016-09-276-2/+11
| | | | | | | | | | | | | | | | When passed to winsys->buffer_create, this flag will indicate that we require a buffer that maps 1:1 with a kernel buffer handle. This is currently set for all textures, since textures can potentially be exported to other processes. This is not a huge loss, since the main purpose of this patch series is to deal with applications that allocate many small buffers. A hypothetical application with tons of tiny textures might still benefit from not setting this flag, but that's not a use case I'm worried about just now. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add RADEON_USAGE_SYNCHRONIZEDNicolai Hähnle2016-09-275-13/+25
| | | | | | | | | | This is really the behavior we want most of the time, but having a SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that OR'ing different flags together always results in stronger guarantees. The parent BOs of sub-allocated buffers will be added unsynchronized. Reviewed-by: Marek Olšák <[email protected]>
* gallium/pipebuffer: add pb_slab utilityNicolai Hähnle2016-09-273-0/+409
| | | | | | | | | | | | | This is a simple framework for slab allocation from buffers that fits into the buffer management scheme of the radeon and amdgpu winsyses where bufmgrs aren't used. The utility knows about different sized allocations and explicitly manages reclaim of allocations that have pending fences. It manages all the free lists but does not actually touch buffer objects directly, relying on callbacks for that. Reviewed-by: Marek Olšák <[email protected]>
* gallium/u_math: add util_logbase2_ceilNicolai Hähnle2016-09-271-0/+12
| | | | | | For finding the exponent of the next power of two. Reviewed-by: Marek Olšák <[email protected]>
* i915g: add dma-buf support to i915_drm_buffer_get_handleNicholas Bishop2016-09-271-0/+6
| | | | | | | | | | | | | | | | The implementation of i915_drm_buffer_get_handle now handles DRM_API_HANDLE_TYPE_FD in the same way that intel_winsys_import_handle does, by calling drm_intel_bo_gem_create_from_prime. Tested by successfully running Chrome's ozone_demo [1] with the ozone-gbm backend on an Intel Pineview M machine. Without this change it fails while trying to create a DMA-BUF. [1] https://chromium.googlesource.com/chromium/src.git/+/master/ui/ozone/demo/ozone_demo.cc Signed-off-by: Nicholas Bishop <[email protected]> [Emil Velikov: Fix coding style] Signed-off-by: Emil Velikov <[email protected]>
* st/dri: check pipe_screen->resource_get_handle() return valueNicholas Bishop2016-09-271-2/+4
| | | | | | | | | | | | | | | | | | | | | Change dri2_query_image to check the return value of resource_get_handle and return GL_FALSE if an error occurs. For reference this is an example callstack that should propagate the error back to the user: i915_drm_buffer_get_handle i915_texture_get_handle u_resource_get_handle_vtbl dri2_query_image gbm_dri_bo_get_fd gbm_bo_get_fd Cc: [email protected] Signed-off-by: Nicholas Bishop <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (v1) [Emil Velikov: Split from larger patch, polish coding style, cc stable] Signed-off-by: Emil Velikov <[email protected]>
* st/va Avoid VBR bitrate calculation overflow v2Andy Furniss2016-09-271-1/+1
| | | | | | | | | | VBR bitrate calc needs 64 bits at high rates. v2: use float. Signed-off-by: Andy Furniss <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
* st/va: Fix vaSyncSurface with no outstanding operationMark Thompson2016-09-271-0/+7
| | | | | | Fixes crash if the application doesn't do what the state tracker expects. Reviewed-by: Christian König <[email protected]>
* nv50/ir: fix comments about instructions infoSamuel Pitoiset2016-09-261-2/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* mesa/st: support lowering multi-planar YUVRob Clark2016-09-265-23/+120
| | | | | | | | | | | | | | | Support multi-planar YUV for external EGLImage's (currently just in the dma-buf import path) by lowering to multiple texture fetch's for each plane and CSC in shader. There was some discussion of alternative approaches for tracking the additional UV or U/V planes: https://lists.freedesktop.org/archives/mesa-dev/2016-September/127832.html They all seemed worse than pipe_resource::next Signed-off-by: Rob Clark <[email protected]>
* nvc0: allow to force compiling programs in debug buildSamuel Pitoiset2016-09-261-9/+10
| | | | | | | | | This adds a new envvar called NV50_PROG_CHIPSET which allows to compile shaders with a different target, especially useful for shader-db. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: drop unused NVISA_XXX_CHIPSET constantsSamuel Pitoiset2016-09-261-2/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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