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* radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPRMarek Olšák2017-09-071-6/+14
* radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPRMarek Olšák2017-09-073-6/+20
* radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HSMarek Olšák2017-09-072-1/+11
* radeonsi: don't read the LS output vertex stride from an SGPR in LSMarek Olšák2017-09-071-4/+21
* radeonsi: don't read the number of TCS out vertices from an SGPR in TCSMarek Olšák2017-09-071-2/+15
* radeonsi: don't always apply the PrimID instancing bug workaround on SIMarek Olšák2017-09-071-1/+1
* radeonsi: remove 2 callbacks from si_shader_contextMarek Olšák2017-09-073-17/+13
* winsys/amdgpu: disable local BOs on RavenMarek Olšák2017-09-071-1/+2
* llvmpipe, tgsi: hook up dx10 gather4 opcodeRoland Scheidegger2017-09-072-8/+25
* llvmpipe, draw: increase shader cache limitsRoland Scheidegger2017-09-072-4/+2
* radeon/uvd: fix the assertion check for YUYV formatLeo Liu2017-09-061-3/+5
* swr/rast: FE/Clipper - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-063-1189/+446
* swr/rast: Remove use of C++14 template variableTim Rowley2017-09-062-6/+14
* swr/rast: SIMD16 FE remove templated immediates workaroundTim Rowley2017-09-061-90/+20
* swr/rast: SIMD16 PA - rename Assemble_simd16 to AssembleTim Rowley2017-09-063-31/+15
* swr/rast: FE/Binner - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-065-1739/+696
* swr/rast: Removed some trailing whitespace caught during reviewTim Rowley2017-09-063-10/+10
* swr: set caps for VB 4-byte alignmentTim Rowley2017-09-061-3/+6
* swr/rast: Allow gather of floats from fetch shader with 2-4GB offsetsTim Rowley2017-09-062-1/+7
* radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bugNicolai Hähnle2017-09-065-24/+85
* amd/common: pass chip_class to ac_dump_regNicolai Hähnle2017-09-061-15/+30
* radeonsi/gfx9: always flush DB metadata on framebuffer changesNicolai Hähnle2017-09-063-4/+14
* svga: move index buffer bind flag assertionCharmaine Lee2017-09-051-3/+3
* svga: avoid emitting redundant SetShaderResources and SetVertexBuffersCharmaine Lee2017-09-052-18/+116
* radeonsi/gfx9: implement primitive binningMarek Olšák2017-09-0510-7/+489
* radeonsi: add more state flags into si_state_dsaMarek Olšák2017-09-052-1/+23
* radeonsi/gfx9: don't use BREAK_BATCH and FLUSH_DFSM if DFSM is disabledMarek Olšák2017-09-052-3/+4
* radeonsi: eliminate PS color outputs when colormask kills themMarek Olšák2017-09-043-0/+6
* gallium/radeon: sort DBG shader flags according to pipe_shader_typeMarek Olšák2017-09-044-35/+17
* radeonsi: ensure cache flushes happen before SET_PREDICATION packetsNicolai Hähnle2017-09-043-9/+18
* radeonsi: fix ARB_transform_feedback_overflow_query on <= VINicolai Hähnle2017-09-043-1/+12
* radeonsi: fix compute shader state dumpingNicolai Hähnle2017-09-041-6/+11
* radeonsi: add an assertion that only two-dimensional constant references are ...Nicolai Hähnle2017-09-041-2/+3
* gallium/radeon: always use two-dimensional constant referencesNicolai Hähnle2017-09-041-18/+18
* gallium/tests: always use two-dimensional constant referencesNicolai Hähnle2017-09-043-10/+10
* pp: always use two-dimensional constant referencesNicolai Hähnle2017-09-041-10/+10
* gallium/hud: always use two-dimensional constant referencesNicolai Hähnle2017-09-041-4/+4
* nine: always generate two-dimensional constant file accessesNicolai Hähnle2017-09-042-7/+5
* tgsi/build: always generate two-dimensional constant file accessesNicolai Hähnle2017-09-042-31/+45
* tgsi/ureg: always emit constants (and their decls) as 2DNicolai Hähnle2017-09-041-15/+7
* gallium: all drivers should accept two-dimensional constant buffer indexingNicolai Hähnle2017-09-042-9/+4
* radeon/uvd: add Define Restart Interval to MJPEG bitstream reconstructionLeo Liu2017-09-021-0/+11
* radeon/uvd: fix MJPEG quantization table indexLeo Liu2017-09-021-1/+1
* freedreno: skip batch-cache for compute shadersRob Clark2017-09-021-7/+1
* swr: Report format max_samples=1 to maintain support for "fake" msaa.Cherniak, Bruce2017-09-011-11/+11
* radeonsi: move si_vm_fault_occured() to AMD common codeSamuel Pitoiset2017-09-011-102/+4
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nvc0: write 0 to pipeline_statistics.cs_invocationsKarol Herbst2017-08-311-0/+1
* llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 loadBen Crocker2017-09-011-2/+28
* gallivm: correct channel shift logic on big endianRay Strode2017-09-011-1/+7
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