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* Revert "radeonsi: reject invalid vertex element formats"Marek Olšák2017-01-201-5/+0
| | | | | | | This reverts commit 9e4d1d8a7c0d60a6975d186944cd870e06f94773. It broke arb_vertex_type_10f_11f_11f_rev-draw-vertices, which has first_non_void == -1.
* gallium: add pipe_screen::resource_changed callback wrappersPhilipp Zabel2017-01-203-0/+47
| | | | | | | | | | Add resource_changed to the ddebug, rbug, and trace wrappers. Since it is optional, there is no need to add it to noop. Signed-off-by: Philipp Zabel <[email protected]> Suggested-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: implement resource_changed to invalidate internal resources derived ↵Philipp Zabel2017-01-201-0/+13
| | | | | | | | | | | | from imported buffers Implement the resource_changed pipe callback to invalidate internal resources derived from imported buffers. This is needed to update the texture for re-imported renderables. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Reviewed-by: Christian Gmeiner <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: initialize seqno of imported resourcesPhilipp Zabel2017-01-201-0/+2
| | | | | | | | | | Imported resources already have contents that we want to be copied to texture resources derived from them. Set initial seqno of imported resources to 1, just as if it had already been rendered to. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* st/dri: ask the driver to update its internal copies on reimportPhilipp Zabel2017-01-201-0/+4
| | | | | | | | | | | | For imported buffers that can't be used directly as a source to the texture samplers, the pipe driver might need to create an internal copy, for example in a different tiling layout. When buffers are reimported they may contain new image data, so the driver internal copies need to be recreated. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* gallium: add pipe_screen::resource_changedPhilipp Zabel2017-01-202-0/+22
| | | | | | | | | | Add a hook to tell drivers that an imported resource may have changed and they need to update their internal derived resources. Signed-off-by: Philipp Zabel <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* gallium/hud: add missing break in hud_cpufreq_graph_install()Samuel Pitoiset2017-01-201-0/+1
| | | | | | | Fixes: e99b9395bef "gallium/hud: Add support for CPU frequency monitoring" Cc: [email protected] Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: reject invalid vertex element formatsMarek Olšák2017-01-191-0/+5
| | | | | | | | This should fix a coverity defect. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* radeonsi: don't forget to add HTILE to the buffer list for texturingMarek Olšák2017-01-191-6/+13
| | | | | | | | | | | | This fixes VM faults. Discovered by Samuel Pitoiset. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98975 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99450 Cc: 17.0 13.0 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* st/vdpau: only send buffers with B8G8R8A8 format to XNayan Deshmukh2017-01-193-3/+11
| | | | | | | | | | | | | | | | PresentPixmap only works if the pixmap depth matches with the window depth, otherwise it returns a BadMatch protocol error. Even if the depths match, the result won't look correctly if the VDPAU RGB component order doesn't match the X11 one so we only allow the X11 format. For other buffers we copy them to a buffer which is send to X. v2: only send buffers with format VDP_RGBA_FORMAT_B8G8R8A8 v3: reword commit message v4: add comment explaining the code Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: fix texture gather on stencil texturesNicolai Hähnle2017-01-191-2/+16
| | | | | | | | | | | | | | | | | | | | | | | At least on VI, texture gather doesn't work with a 24_8 data format, so use 8_8_8_8 and a modified swizzle instead. A bit of background: When creating a GL_STENCIL_INDEX8 texture, we select the X24S8 pipe format because we don't support stencil-only render targets properly. With mip-mapping this can lead to a setup where the tiling is incompatible with stencil texturing, and a flushed stencil texture is used. For the flushed stencil, a literal X24S8 is used because there were issues with an 8bpp DB->CB copy. Longer term, it would be good if we could get away from these workarounds, i.e. properly support an S8 format for stencil-only rendering and flushed stencil. Since stencil texturing is somewhat rare, it's not a high priority. Fixes GL45-CTS.texture_cube_map_array.sampling. Cc: 17.0 <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Edward O'Callaghan <[email protected]>
* radeonsi: Always leave poly_offset in a valid stateZachary Michaels2017-01-191-1/+3
| | | | | | | | | | This commit makes si_update_poly_offset set poly_offset to NULL if uses_poly_offset is false. This way poly_offset either points into the currently queued rasterizer, or it is NULL. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99451 Cc: "13.0 17.0" <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: use #ifdef not #if for PIPE_ARCH_BIG_ENDIANDave Airlie2017-01-191-1/+1
| | | | | | | | This fixes the build on ppc/s390. Reviewed-by: Roland Scheidegger <[email protected]> Cc: "17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: determine in advance which VBOs should be added to the buffer listMarek Olšák2017-01-183-4/+11
| | | | | | v2: now it should be correct Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use fewer pointer dereferences in upload_vertex_buffer_descriptorsMarek Olšák2017-01-181-8/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: reject invalid vertex buffer indices at state creationMarek Olšák2017-01-182-5/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use a global dirty mask for shader pointersMarek Olšák2017-01-184-41/+51
| | | | | | Only vertex buffers use a separate bool flag. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use a bitmask-based loop in si_decompress_texturesMarek Olšák2017-01-183-7/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: skip an unnecessary mutex lock for L2 prefetchesMarek Olšák2017-01-181-5/+7
| | | | | | the mutex lock is inside util_range_add. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: si_cp_dma_prepare is a no-op for L2 prefetchesMarek Olšák2017-01-182-5/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add SI_CPDMA_SKIP_BO_LIST_UPDATEMarek Olšák2017-01-182-10/+15
| | | | | | | the next commit will use it in a clever way, because the CP DMA prefetch doesn't need this. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use the correct target machine when building shader variantsMarek Olšák2017-01-182-14/+29
| | | | | | | | | | If the shader selector is created with a different context than the shader variant, we should use the calling context's target machine for the shader variant. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99419 Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move shader pipe context state into a separate structureMarek Olšák2017-01-182-14/+22
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* Revert "etnaviv: Fake occlusion query capability"Christian Gmeiner2017-01-181-3/+2
| | | | | | | | | | This reverts commit b7ac0f567123c96b5cd9e3485b963a5c0a0db66a. This is a half baked solution needs some rework to fixes issues with reported counter bits (GL_QUERY_COUNTER_BITS_ARB). Also it enables PIPE_CAP_QUERY_TIME_ELAPSED accidently. Signed-off-by: Christian Gmeiner <[email protected]>
* android: ac/debug: move sid_tables.h generation and IB decode to amd/commonMauro Rossi2017-01-181-12/+3
| | | | | | | | | | | | | | | This patch is the porting to android of the following commits: b838f64 "ac/debug: Move sid_tables.h generation to common code." 0ef1b4d "ac/debug: Move IB decode to common code." Fixes android building errors due to sid_tables.h and ac_debug.c, ac_debug.h moved to amd/common Tested by building nougat-x86 Acked-by: Nicolai Hähnle <[email protected]> Acked-by: Emil Velikov <[email protected]>
* android: gallium/auxiliary: fix building error in Android 7.0Mauro Rossi2017-01-181-1/+1
| | | | | | | | | | | | | | | | | | Conditional libLLVMCore static library dependency is added, for the case when MESA_ENABLE_LLVM is true Fixes the following building error with Android 7.0: In file included from external/mesa/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp:62: ... external/llvm/include/llvm/IR/Attributes.h:68:14: fatal error: 'llvm/IR/Attributes.inc' file not found #include "llvm/IR/Attributes.inc" ^ 1 error generated. Reviewed-by: Emil Velikov <[email protected]>
* android: radeonsi: fix LLVMInitializeAMDGPU* functions declarationMauro Rossi2017-01-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLVMInitializeAMDGPU* functions need to be explicitly declared and mesa expects them via <llvm-c/Target.h> header, but LLVM needs to be instructed to invoke its own LLVM_TARGET(AMDGPU) macro, or the functions will not be available. A new llvm cflag (-DFORCE_BUILD_AMDGPU) serves this purpose, the same mechanism is used also by other llvm targets e.g. FORCE_BUILD_ARM A necessary prerequisite is to have AMDGPU target handled accordingly in llvm config files i.e. {Target,AsmParser,AsmPrinter}.def for llvm device build includes. This avoids the following building errors: external/mesa/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c:129:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTargetInfo' is invalid in C99 [-Werror,-Wimplicit-function-declaration] LLVMInitializeAMDGPUTargetInfo(); ^ external/mesa/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c:130:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTarget' is invalid in C99 [-Werror,-Wimplicit-function-declaration] LLVMInitializeAMDGPUTarget(); ^ external/mesa/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c:131:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTargetMC' is invalid in C99 [-Werror,-Wimplicit-function-declaration] LLVMInitializeAMDGPUTargetMC(); ^ external/mesa/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c:132:2: error: implicit declaration of function 'LLVMInitializeAMDGPUAsmPrinter' is invalid in C99 [-Werror,-Wimplicit-function-declaration] LLVMInitializeAMDGPUAsmPrinter(); ^ Acked-by: Nicolai Hähnle <[email protected]> Acked-by: Emil Velikov <[email protected]>
* android: radeon: fix LLVMInitializeAMDGPU* functions declarationMauro Rossi2017-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLVMInitializeAMDGPU* functions need to be explicitly declared and mesa expects them via <llvm-c/Target.h> header, but LLVM needs to be instructed to invoke its own LLVM_TARGET(AMDGPU) macro, or the functions will not be available. A new llvm cflag (-DFORCE_BUILD_AMDGPU) serves this purpose, the same mechanism is used also by other llvm targets e.g. FORCE_BUILD_ARM A necessary prerequisite is to have AMDGPU target handled accordingly in llvm config files i.e. {Target,AsmParser,AsmPrinter}.def for llvm device build includes. This avoids the following building errors: external/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c:121:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTargetInfo' [-Werror=implicit-function-declaration] LLVMInitializeAMDGPUTargetInfo(); ^ external/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c:122:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTarget' [-Werror=implicit-function-declaration] LLVMInitializeAMDGPUTarget(); ^ external/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c:123:2: error: implicit declaration of function 'LLVMInitializeAMDGPUTargetMC' [-Werror=implicit-function-declaration] LLVMInitializeAMDGPUTargetMC(); ^ external/mesa/src/gallium/drivers/radeon/radeon_llvm_emit.c:124:2: error: implicit declaration of function 'LLVMInitializeAMDGPUAsmPrinter' [-Werror=implicit-function-declaration] LLVMInitializeAMDGPUAsmPrinter(); ^ Acked-by: Nicolai Hähnle <[email protected]> Acked-by: Emil Velikov <[email protected]>
* nouveau: remove always false argument in nouveau_fence_new()Emil Velikov2017-01-185-11/+6
| | | | | | | | | No point in having the extra argument considering that it's effectively unused since the function was introduced. Cc: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: correctly manage libsensors link flagsEmil Velikov2017-01-182-2/+1
| | | | | | | | | | We should be using LIBS rather than the LDFLAGS variable. Furthermore try to keep the linking to the final stage, rather than intermetent static library. Cc: Steven Toth <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: Fake occlusion query capabilityWladimir J. van der Laan2017-01-181-2/+3
| | | | | | | | | | | | | This enables the PIPE_CAP_OCCLUSION_QUERY capability without adding an occlusion query type. This is necessary to get Mesa to report desktop GL 2.0 support (to run exciting things such as ioq3's OpenGL 2 renderer), and should be valid because exposing the capability does not guarantee that any counters are actually implemented. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: add flags parameter to texture barrierChristian Gmeiner2017-01-181-1/+1
| | | | | | Fixes compile warning introduced by commit a1c848. Signed-off-by: Christian Gmeiner <[email protected]>
* etnaviv: handle PIPE_CAP_TGSI_FS_FBFETCHChristian Gmeiner2017-01-181-0/+1
| | | | | | Fixes compile warning introduced by commit ee3ebe. Signed-off-by: Christian Gmeiner <[email protected]>
* gallivm: (trivial) fix copy/paste bug with big endian codeRoland Scheidegger2017-01-181-2/+4
| | | | | | 8bd67a35c50e68c21aed043de11e095c284d151a introduced using undefined variable on big endian archs due to copy/paste bug. (compile hack tested only)
* configure.ac: Revert recent HAVE_LLVM changes.Jose Fonseca2017-01-185-12/+12
| | | | | | | | | | | | | | | | This reverts changes 903eb09b5fb78d47d0f8a4bdf826a113ca2aff40..1a0aa468f354f0ee94dd383cd40ae915584624aa: Tobias Droste (5): configure.ac: Rename MESA_LLVM to FOUND_LLVM configure.ac: Only set LLVM_LIBS if LLVM is used configure.ac: Only define HAVE_LLVM if LLVM is used configure.ac: Set and use HAVE_GALLIUM_LLVM define configure.ac: Don't check LLVM version in gallium_require_llvm They break scons build, and I'm not convinced this is the right fix. In particular changing HAVE_LLVM in the C code is something I'd rather avoid no matter what. So it's better to discuss without the pressure of broken builds.
* configure.ac: Set and use HAVE_GALLIUM_LLVM defineTobias Droste2017-01-185-12/+12
| | | | | | | | | | | | Gallium code used HAVE_LLVM to check if it needs to compile code for LLVM in header and source files. With the new logic HAVE_LLVM is always set. Use extra define to figure out if LLVM is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99010 Signed-off-by: Tobias Droste <[email protected]>
* gallivm: Cleanup USE_MCJIT.Jose Fonseca2017-01-181-10/+25
| | | | | | | Split USE_MCJIT macro dual nature into a separate constant time define and a run-time variable. Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: for the tess barrier, only use emit_waitcnt on SI and LLVM 3.9+Marek Olšák2017-01-171-2/+5
| | | | | | Cc: 17.0 13.0 <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/vdpau: remove the delayed rendering hack(v1.1)Nayan Deshmukh2017-01-176-141/+52
| | | | | | | | | | the hack was introduced to avoid an extra copying but now with dri3 we don't need it anymore v1.1: rebasing Signed-off-by: Nayan Deshmukh <[email protected]> Acked-by: Christian König <[email protected]>
* st/vdpau: use dri3 to directly send the buffer to X(v2)Nayan Deshmukh2017-01-172-27/+33
| | | | | | | | | | | | this avoids an extra copy which occurs in case of dri2 v1.1: fallback to dri2 if dri3 fails to initialize v2: add PIPE_BIND_SCANOUT to output buffers as they will be send to X server directly (Michel) Suggested-by: Christian König <[email protected]> Tested-by: Andy Furniss <[email protected]> Signed-off-by: Nayan Deshmukh <[email protected]>
* vl/dri3: use external texture as back buffers(v4)Nayan Deshmukh2017-01-172-17/+114
| | | | | | | | | | | | | | | | | | | | | dri3 allows us to send handle of a texture directly to X so this patch allows a state tracker to directly send its texture to X to be used as back buffer and avoids extra copying v2: use clip width/height to display a portion of the surface v3: remove redundant variables, fix wrapping, rename variables handle vaapi path v3.1: we need clip_width/height for every frame so we don't need to maintain it for each buffer instead use a global variable v4: In case of single gpu we can cache the buffers as applications use constant number of buffer and we can avoid calls to present extension for every frame Reviewed and Suggested-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]> Tested-by: Andy Furniss <[email protected]> Signed-off-by: Nayan Deshmukh <[email protected]>
* nv50/ir: optimize shl + andIlia Mirkin2017-01-161-0/+11
| | | | | | | | | | | | | | | | | Address loading can often end up as shl + shr + shl combinations. The latter two are equal shifts, which get converted into an and mask. However if the previous shl is more than the mask is trying to remove (in terms of low bits), we can just remove the and entirely. This reduces some large shaders by as many as 3% of instructions (out of 2K). total instructions in shared programs : 6495509 -> 6491076 (-0.07%) total gprs used in shared programs : 954621 -> 954623 (0.00%) local gpr inst bytes helped 0 0 1014 1014 hurt 0 2 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-169-6/+172
| | | | | | | | | | | | We don't need to support all the color buffers for advanced blend, just cb0. For Fermi, we use the special binding slots so that we don't overlap with user textures, while Kepler+ gets a dedicated position for the fb handle in the driver constbuf. This logic is only triggered when a FBFETCH is actually present so it should be a no-op most of the time. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add flags parameter to texture barrierIlia Mirkin2017-01-1613-15/+23
| | | | | | | | This is so that we can differentiate between flushing any framebuffer reading caches from regular sampler caches. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin2017-01-1617-2/+20
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add FBFETCH opcode to retrieve the current sample valueIlia Mirkin2017-01-163-2/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwellIlia Mirkin2017-01-161-2/+2
| | | | | | | This had been updated in one place but not the other. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nv50/ir: handle new DDIV op which will be used for double divisionsIlia Mirkin2017-01-161-0/+3
| | | | | | | The existing lowering is in place to lower that to RCP + MUL, or fancier things down the line if necessary. Signed-off-by: Ilia Mirkin <[email protected]>
* tgsi: add DDIV instructionNicolai Hähnle2017-01-164-1/+17
| | | | | | | | | Double-precision division, to allow more precision than a DRCP + DMUL sequence. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix R600_DEBUG=nooptvariantNicolai Hähnle2017-01-161-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Vedran Miletić <[email protected]>
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