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* nvc0/ir: add kepler+ support for indirect texture referencesIlia Mirkin2014-08-111-7/+27
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add base tex offset for fermi indirect tex caseIlia Mirkin2014-08-111-2/+10
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: Flip which primitives are considered front-facing.Eric Anholt2014-08-111-1/+1
| | | | This mostly fixes glxgears rendering.
* vc4: Don't forget to set the depth clear value in the packet.Eric Anholt2014-08-111-1/+1
| | | | This gets glxgears partially rendering again.
* vc4: Add support for gl_FragCoord.Eric Anholt2014-08-115-4/+76
| | | | | | | This isn't passing all tests (glsl-fs-fragcoord-zw-ortho, for example), but it does get a bunch more tests passing. v2: Rebase on helpers change.
* vc4: Refactor shader input setup again.Eric Anholt2014-08-111-17/+24
| | | | This makes some space for handling special inputs like fragcoords.
* vc4: Clean up the tile alloc buffer size.Eric Anholt2014-08-111-1/+9
| | | | | | | This prevents some simulator assertion failures, but it does mean (since I've dropped the "* 16" padding) that on real hardware you need a kernel that does overflow memory management (currently, "drm/vc4: Add support for binner overflow memory allocation." in my kernel tree).
* vc4: Clarify some values implicitly chosen for binning config.Eric Anholt2014-08-111-1/+4
| | | | These #defines are 0, but it should help make math above make more sense.
* vc4: Improve simulator memory allocation.Eric Anholt2014-08-111-4/+20
| | | | This should reduce a bunch of spurious failures in sim.
* vc4: Handle stride==0 in VBO validationEric Anholt2014-08-111-7/+9
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* vc4: Stash some debug code for looking at what BOs are at what hindex.Eric Anholt2014-08-112-0/+5
| | | | When you're debugging validation, it's nice to know what the BOs are for.
* vc4: Use GEM under simulation even for non-winsys BOs.Eric Anholt2014-08-112-14/+9
| | | | | | | In addition to reducing sim-specific code, it also avoids our local handle allocation conflicting with the host GEM's handle numbering, which was causing vc4_gem_hindex() to not distinguish between winsys BOs and the same-numbered non-winsys bo.
* vc4: Don't forget to unmap the GEM BO when freeing.Eric Anholt2014-08-111-0/+3
| | | | Otherwise it'll stick around forever.
* vc4: Add validation of raster-format textures.Eric Anholt2014-08-112-17/+96
| | | | | | ... and reject everything else, for now. v2: Rebase on v2 of the rendering config validation change.
* vc4: Drop VC4_PACKET_PRIMITIVE_LIST_FORMAT.Eric Anholt2014-08-112-4/+4
| | | | | | It's not relevant to our command streams any more. v2: Fix indentation and a typo in the comment.
* vc4: Add validation that vertex indices don't overflow VBO bounds.Eric Anholt2014-08-112-18/+71
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* vc4: Fix the shader record size for extended strides.Eric Anholt2014-08-111-0/+1
| | | | | It turns out they aren't packed when attributes are missing, according to both docs and simulation.
* vc4: Fix the shader record size for extended strides.Eric Anholt2014-08-111-1/+4
| | | | | | | It turns out they aren't packed when attributes are missing, according to both docs and simulation. v2: Drop unused variable.
* vc4: Add a bunch of validation of render mode configuration.Eric Anholt2014-08-113-11/+151
| | | | v2: Fix a build break after some previous rebase.
* vc4: Store the (currently always linear) tiling format in the resource.Eric Anholt2014-08-114-8/+25
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* vc4: Add a bunch of validation of the binning mode config.Eric Anholt2014-08-112-17/+140
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* vc4: Validate that the same BO doesn't get reused for different purposes.Eric Anholt2014-08-113-37/+81
| | | | | | | | | We don't care if things like vertex data get smashed by render target data, but we do need to make sure that shader code doesn't get rendered to. v2: Fix overflowing read of gl_relocs[] that incorrect flagged of some VBOs as shader code.
* vc4: Use the packet #defines in the kernel validation code.Eric Anholt2014-08-111-45/+40
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* vc4: Rename GEM_HANDLES to be in a namespace.Eric Anholt2014-08-112-2/+8
| | | | | It's not a real VC4 hardware packet, but I've put in a comment to explain it.
* vc4: Clean up TMU write validation.Eric Anholt2014-08-111-77/+64
| | | | | | The comment conflicted with the support in the code, so I moved the TMU write validation to where the comment was, and dropped some dead arguments from the functions while changing their signatures.
* vc4: Update a comment about shader validationEric Anholt2014-08-111-4/+2
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* vc4: Add proper translation from Zc to Zs for vertex output.Eric Anholt2014-08-112-1/+18
| | | | This fixes the remaining failure in depthfunc.
* vc4: Add support for depth clears and tests within a tile.Eric Anholt2014-08-1110-12/+65
| | | | | | | | | This doesn't load/store the Z contents across submits yet. It also disables early Z, since it's going to require tracking of Z functions across multiple state updates to track the early Z direction and whether it can be used. v2: Move the key setup to before the search for the key.
* vc4: Avoid flushing when mapping buffers that aren't in the batch.Eric Anholt2014-08-113-1/+50
| | | | | This should prevent a bunch of unnecessary flushes for things like updating immediate vertex data.
* vc4: Drop the flush at the end of the drawEric Anholt2014-08-112-2/+2
| | | | Now we actally get multiple draw calls per submit.
* vc4: Align following shader recs to 16 bytes.Eric Anholt2014-08-112-2/+10
| | | | | Otherwise, the low address bits will end up being interpreted as attribute counts.
* vc4: Fix a potential src buffer overflow in shader rec validation.Eric Anholt2014-08-111-0/+1
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* vc4: Keep a reference to BOs queued for rendering.Eric Anholt2014-08-113-8/+4
| | | | | | Otherwise, once we're not flushing at the end of every draw, we'll free things like gallium resources, and free the backing GEM object, before we've flushed the rendering using it to the kernel.
* vc4: Compute the proper end address of the relocated command lists.Eric Anholt2014-08-112-2/+5
| | | | | | | | | render_cl_size/bin_cl_size includes relocations, while the hardware buffer doesn't. If you don't emit a HALT packet, the command parser continues until the end register's value. We can't allow executing unvalidated buffer contents (and it's actually harmful in the render lists Mesa is emitting, since VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF doesn't trigger a halt).
* vc4: Walk tiles horizontally, then vertically.Eric Anholt2014-08-111-2/+2
| | | | | I was confused looking at my addresses in dumps because I was seeing the tile branch offsets jumping all over.
* vc4: Track clears veresus uncleared draws, and the clear color.Eric Anholt2014-08-113-34/+117
| | | | | | This is a step toward queueing more than one draw per frame. Fixes piglit attribute0 test, since we get a working clear color now.
* vc4: Move the rest of RCL setup to flush time.Eric Anholt2014-08-112-33/+30
| | | | | We only want to set up render target config and clear colors once per frame.
* vc4: Move render command list calls to vc4_flush()Eric Anholt2014-08-112-40/+43
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* vc4: Move bin command list ending commands to vc4_flush()Eric Anholt2014-08-112-4/+4
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* vc4: Rename fields in the kernel interface.Eric Anholt2014-08-113-32/+32
| | | | | I decided I didn't like "len" compared to "size", and I keep typing shader_rec instead of shader_record[s] elsewhere, so make it consistent.
* vc4: Fix things to validate more than one shader state in a submit.Eric Anholt2014-08-113-67/+78
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* vc4: Rewrite the kernel ABI to support texture uniform relocation.Eric Anholt2014-08-1110-97/+608
| | | | | | | | | | This required building a shader parser that would walk the program to find where the texturing-related uniforms are in the uniforms stream. Note that as of this commit, a new kernel is required for rendering on actual VC4 hardware (currently that commit is named "drm/vc4: Introduce shader validation and better command stream validation.", but is likely to be squashed as part of an eventual merge of the kernel driver).
* vc4: Add docs for the drm interfaceEric Anholt2014-08-111-9/+61
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* vc4: Add load/store to the validatorEric Anholt2014-08-111-11/+9
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* vc4: Switch simulator to using kernel validatorEric Anholt2014-08-1111-62/+840
| | | | | | | | This ensures that when I'm using the simulator, I get a closer match to what behavior on real hardware will be. It lets me rapidly iterate on the kernel validation code (which otherwise has a several-minute turnaround time), and helps catch buffer overflow bugs in the userspace driver faster.
* vc4: Drop pointless shader state structEric Anholt2014-08-112-14/+10
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* vc4: Add support for texture rectanglesEric Anholt2014-08-112-0/+42
| | | | v2: Rebase on helpers change.
* vc4: Add support for texturing (under simulation)Eric Anholt2014-08-118-13/+277
| | | | | | | | Only rgba8888 works, and only a single texture unit, and it's only under simulation because I haven't built the kernel interface yet. v2: Rebase on helpers. v3: Fold in the don't-break-the-arm-build fix.
* vc4: Drop PIPE_SHADER_CAP_MAX_ADDRSEric Anholt2014-08-111-2/+0
| | | | Fixes the build since c10332bbb8889d733bdaa729ef23cbd90176b55d
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-1115-35/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
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