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* freedreno/a6xx: fix mem2gmem for zsbufRob Clark2018-09-051-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/batch: fix crash in !reorder caseRob Clark2018-09-051-2/+8
| | | | | | We aren't using the batch-cache if reorder==false. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: better compile_error() printingRob Clark2018-09-051-2/+16
| | | | | | Try to show the error at the appropriate line of nir Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: bordercolor fixesRob Clark2018-09-051-4/+25
| | | | | | | | | Port fixes from a5xx (f0715442) TODO maybe this should move to shared code, since it seems to be the same. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix context teardown harderRob Clark2018-09-054-8/+8
| | | | | | | | The border_color_uploaders need to be torn down before the transfer_pool is destroyed. Fixes: e11e9d63943 freedreno: fix context teardown race Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ignore unused inputsRob Clark2018-09-051-1/+29
| | | | | | | | | | We could end up w/ inputs larger than vec4, simply because unused inputs are not split. Fixes things like dEQP-GLES31.functional.separate_shader.random.77 (and probably a handful of others) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix debug build crashRob Clark2018-09-051-0/+7
| | | | | | Porting 0c8d9e923aa9239e20f9bc969faf9caa0b85237f to a6xx. Signed-off-by: Rob Clark <[email protected]>
* svga: rename face to layer_faceCharmaine Lee2018-09-051-22/+25
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: encode sample count in resource declarationsBrian Paul2018-09-054-0/+6
| | | | | | No regressions before the corresponding host-side change. Reviewed-by: Neha Bhende <[email protected]>
* svga: sync with upstream changes to surface flagsCharmaine Lee2018-09-059-14/+19
| | | | | | | | | SVGA device now supports 64 bits surface flags. This patch updates the winsys interface to allow 64 bits surface flags. The linux winsys layer will for now only honor the lower 32 bits of the surface flags. Reviewed-by: Brian Paul <[email protected]>
* svga: avoid try_blit() for some depth formats on non vgpu10.Neha Bhende2018-09-051-0/+13
| | | | | | | | | | | | | On non vgpu10, driver doesn't support util_blitter_blit for SVGA3D_Z_D16, SVGA3D_Z_D24x8, SVGA3D_Z_D24S8. Patch fixes following piglit tests regression on hwv8 caused by commit 27bf35caea5e: spec@arb_depth_texture@fbo-depth-gl-depth-component16-blit spec@arb_depth_texture@fbo-depth-gl-depth-component24-blit spec@arb_depth_texture@fbo-depth-gl-depth-component32-blit Tested with mtt-piglit on hw 8,9,10,11,13 and mtt-glretrace on windows and linux. Reviewed-by: Charmaine Lee <[email protected]>
* svga: convert dst format to linear when blending is enabled.Neha Bhende2018-09-051-1/+3
| | | | | | | | | | | When blending is enabled, framebuffer colorspace has to be linear. Previously, we never hit this case because we were not supporting sRGB drawable. Previous patch added that support. Tested with mtt glretrace, viewperf, piglit, conform. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga: Avoid cap2 code path for nowNeha Bhende2018-09-051-13/+5
| | | | | | | CAP2 functionality is not yet part of vmwgfx. This is causing unnecessary dmesg error messages. Reviewed-by: Charmaine Lee <[email protected]>
* svga: start using SVGA3dCmdIntraSurfaceCopy command for svga_blit.Neha Bhende2018-09-051-0/+112
| | | | | | | | | | | | | Basically, SVGA3dCmdIntraSurfaceCopy command allow copying when source and destination are same. Tested with MTT piglit, glretrace, viewperf, conform v2: changes as per Charmaine's comment v3: changes as per Charmaine's comment Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga/winsys: Add cap2 support in winsysNeha Bhende2018-09-054-2/+38
| | | | | Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: Add SVGA3dCmdIntraSurfaceCopy command support in OpenGL driverNeha Bhende2018-09-053-0/+49
| | | | | | | v2: changes as per Charmaine's comment Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: update device header files from upstreamBrian Paul2018-09-0515-196/+569
| | | | | | This is a squash commit of several earlier patches. Signed-off-by: Brian Paul <[email protected]>
* winsys/drm: Fix assert when try to accumulate an invalid fdCharmaine Lee2018-09-051-2/+7
| | | | | | | | | | This patch makes sure there is a valid fd before merging it to the context's fd in vmw_svga_winsys_fence_server_sync(). This fixes the assert running webot. No regression running kmscube. Reviewed-by: Sinclair Yeh <[email protected]>
* winsys/virgl/vtest: Correct off-by-one error in resource allocationGert Wollny2018-09-051-4/+9
| | | | | | | The resource bo array must already extended when the target index is equal to the current size of the array. Signed-off-by: Gert Wollny <[email protected]>
* winsys/virgl: Initialize value to silence valgrindGert Wollny2018-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | Silences: Conditional jump or move depends on uninitialised value(s) at 0xB72F2C0: virgl_drm_winsys_create (virgl_drm_winsys.c:854) by 0xB72F2C0: virgl_drm_screen_create (virgl_drm_winsys.c:926) by 0xB21C885: pipe_virgl_create_screen (drm_helper.h:275) by 0xB7201F0: pipe_loader_create_screen (pipe_loader.c:137) by 0xB639C91: dri2_init_screen (dri2.c:2112) by 0xB634F68: driCreateNewScreen2 (dri_util.c:153) by 0x63023E6: dri3_create_screen (dri3_glx.c:893) by 0x62D35BD: AllocAndFetchScreenConfigs (glxext.c:820) by 0x62D35BD: __glXInitialize (glxext.c:946) by 0x62CECB3: GetGLXPrivScreenConfig (glxcmds.c:174) by 0x62CF69C: glXQueryExtensionsString (glxcmds.c:1304) by 0x60AA7D9: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.5.2) by 0x4F81450: wfl_checked_display_connect (piglit-util-waffle.h:74) by 0x4F829E0: piglit_wfl_framework_init (piglit_wfl_framework.c:627) Signed-off-by: Gert Wollny <[email protected]>
* winsys/virgl: correct resource and handle allocation (v2)Gert Wollny2018-09-051-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes crash with piglit/bin/map_buffer_range-invalidate CopyBufferSubData \ increment-offset -auto -fbo * Resize the resource storage already when the count is equal to the allocated size, fixes: Invalid write of size 8 at 0xB72E4CF: virgl_drm_add_res (virgl_drm_winsys.c:629) by 0xB72E4CF: virgl_drm_emit_res (virgl_drm_winsys.c:663) by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776) by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585) by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940) by 0x109A1E: upload (invalidate.c:169) by 0x109C2F: piglit_display (invalidate.c:215) by 0x4F80FBE: run_test (piglit_fbo_framework.c:52) by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229) by 0x10949D: main (invalidate.c:47) Address 0xbe07d30 is 0 bytes after a block of size 4,096 alloc'd at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) by 0xB72DAAF: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:567) * Also resize the space allocated for the handles, fixes: Invalid write of size 4 at 0xB72E4F0: virgl_drm_add_res (virgl_drm_winsys.c:631) by 0xB72E4F0: virgl_drm_emit_res (virgl_drm_winsys.c:663) by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776) by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585) by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940) by 0x109A1E: upload (invalidate.c:169) by 0x109C2F: piglit_display (invalidate.c:215) by 0x4F80FBE: run_test (piglit_fbo_framework.c:52) by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229) by 0x10949D: main (invalidate.c:47) Address 0xbe08570 is 0 bytes after a block of size 2,048 alloc'd at 0x4C2FB0F: malloc ( in /usr/lib/valgrind/vgpreload_memcheck-amd64- linux.so) by 0xB72DAC8: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:572) Fixes: 4b15b5e803e ("virgl: resize resource bo allocation if we need to.") v2: - Use REALLOC macro and avoid memory leak when re-allocation fails - add Fixes tag (both Emil Velikov) - reorder commit message Signed-off-by: Gert Wollny <[email protected]>
* virgl: use hw-atomics instead of in-ssbo onesTomeu Vizoso2018-09-057-2/+89
| | | | | | | | Emulating atomics on top of ssbos can lead to too small max SSBO count, so let's use the hw-atomics mechanism to expose atomic buffers instead. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* virgl: update minor differences to upstream headerErik Faye-Lund2018-09-051-1/+1
| | | | | | | | | | | virgl_protocol.h is considered to have it's upstream in the virglrenderer repository, and somehow these minor differences has crept in. Let's sync with the upstream to avoid this. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium: add PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER{S,_BUFFERS}Erik Faye-Lund2018-09-054-0/+19
| | | | | | | | | | | | | | This moves the evergreen-specific max-sizes out as a driver-cap, so other drivers with less strict requirements also can use hw-atomics. Remove ssbo_atomic as it's no longer needed. We should now be able to use hw-atomics for some stages and not for other, if needed. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium: add PIPE_CAP_MAX_COMBINED_SHADER_BUFFERSErik Faye-Lund2018-09-054-0/+9
| | | | | | | | | | | This gets rid of a r600 specific hack in the state-tracker, and prepares for other drivers to be able to use hw-atomics. While we're at it, clean up some indentation in the various drivers. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium/u_threaded: increase batch size to increase performanceMarek Olšák2018-09-041-1/+1
| | | | | | | | | This reduces mutex overhead. radeonsi: +4.4% performance with piglit/drawoverhead, DrawElements, Ryzen X1700 iris_dri.so: +14% with piglit/drawoverhead, DrawArrays, i7 7700HQ. Acked-by: Kenneth Graunke <[email protected]>
* st/vdpau: silence an unitialized-variable warningMarek Olšák2018-09-041-1/+1
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* u_vbuf: Fix leakErnestas Kulik2018-09-041-0/+1
| | | | | | | | | Reported by Coverity: data is heap-allocated, but only freed in the info->index_size != 0 branch. Signed-off-by: Ernestas Kulik <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Cc: 18.2 <[email protected]>
* freedreno: Drop a bunch of duplicated gallium PIPE_CAP default code.Eric Anholt2018-09-041-108/+2
| | | | | | | | | Now that we have the util function for the default values, we can get rid of the boilerplate. v2: Rebase on new gallium caps Reviewed-by: Rob Clark <[email protected]> (v1)
* v3d: Drop a bunch of duplicated gallium PIPE_CAP default code.Eric Anholt2018-09-041-151/+0
| | | | | | | Now that we have the util function for the default values, we can get rid of the boilerplate. v2: Rebase on new gallium caps
* vc4: Drop a bunch of duplicated gallium PIPE_CAP default code.Eric Anholt2018-09-042-184/+1
| | | | | | | | Now that we have the util function for the default values, we can get rid of the boilerplate. v2: drop GLSL level in favor of defaults. v3: Rebase on new gallium caps
* gallium: Add a helper for implementing PIPE_CAP_* default values.Eric Anholt2018-09-0419-35/+403
| | | | | | | | | | | | | | | | | | One of the pains of implementing a gallium driver is filling in a million pipe caps you don't know about yet when you're just starting out. One of the pains of working on gallium is copy-and-pasting your new PIPE_CAP into each driver. We can fix both of these by having each driver call into the default helper from their default case, so that both sides can ignore each other until they need to. v2: fix i915g build, revert swr change to avoid breaking scons build (https://travis-ci.org/anholt/mesa/jobs/419739857) v3: Rebase on 3 new gallium caps. Reviewed-by: Marek Olšák <[email protected]> (v1) Cc: Bruce Cherniak <[email protected]> Cc: George Kyriazis <[email protected]> Cc: Kenneth Graunke <[email protected]>
* imx: make use of loader_open_render_node(..) helperChristian Gmeiner2018-08-311-1/+2
| | | | | | | Gets rid of hard-coded gpu device path. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* tegra: make use loader_open_render_node(..) helperChristian Gmeiner2018-08-311-59/+2
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* tegra: fix memory leakChristian Gmeiner2018-08-311-0/+1
| | | | | | Fixes: 1755f608f52 ("tegra: Initial support") Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/dri: Don't expose sRGB formats to clientsDaniel Stone2018-08-311-0/+6
| | | | | | | | | | | | | | Though the SARGB8888 format is used internally through its FourCC value, it is not a real format as defined by drm_fourcc.h; it cannot be used with KMS or other interfaces expecting drm_fourcc.h format codes. Ensure we don't advertise it through the dmabuf format/modifier query interfaces, preventing us from tripping over an assert. Signed-off-by: Daniel Stone <[email protected]> Reported-by: Michel Dänzer <[email protected]> Fixes: 8c1b9882b2e0 ("egl/dri2: Guard against invalid fourcc formats") Acked-by: Jason Ekstrand <[email protected]>
* radeonsi: fix regression in indirect input swizzles.Dave Airlie2018-08-311-2/+5
| | | | | | | | | This fixes: tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3.shader_test since I reworked the 64-bit swizzles. Fixes: bb17ae49ee2 (gallivm: allow to pass two swizzles into fetches.) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix tess/gs fetchs for new swizzle.Dave Airlie2018-08-311-5/+8
| | | | | | | | I have piglit results from my machine, but I must have messed up, and not built mesa in between properly. Fixes: bb17ae49ee2 (gallivm: allow to pass two swizzles into fetches.) Reviewed-by: Marek Olšák <[email protected]>
* gallivm: Detect VSX separately from AltivecVicki Pfau2018-08-303-19/+17
| | | | | | | | | | Previously gallivm would attempt to use VSX instructions on all systems where it detected that Altivec is supported; however, VSX was added to POWER long after Altivec, causing lots of crashes on older POWER/PPC hardware, e.g. PPC Macs. By detecting VSX separately from Altivec we can automatically disable it on hardware that supports Altivec but not VSX Signed-off-by: Vicki Pfau <[email protected]>
* nv50: bump compat glsl level to same as coreIlia Mirkin2018-08-291-1/+1
| | | | | | | Passes the compat piglits. I'm sure that there will be odd issues that aren't caught by them, but at least it should basically work. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: bump compat GLSL version to match coreIlia Mirkin2018-08-291-1/+1
| | | | | | This passes the handful of tests in piglit. Signed-off-by: Ilia Mirkin <[email protected]>
* st/mesa, gallium: add a workaround for No Mans SkyTimothy Arceri2018-08-303-0/+4
| | | | | | | | The spec seems clear this is not allowed but the Nvidia binary forces apps to add layout qualifiers so this works around the issue for No Mans Sky until the CTS can be sorted out. Reviewed-by: Marek Olšák <[email protected]>
* gallivm: allow to pass two swizzles into fetches.Dave Airlie2018-08-304-41/+79
| | | | | | | | | | | | This hijacks the top 16-bits of swizzle, to pass in the swizzle for the second channel. This fixes handling .yx swizzles of 64-bit values. This should fixup radeonsi and llvmpipe. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add radeonsi_zerovram driconfig optionTimothy Arceri2018-08-302-3/+8
| | | | | | | More and more games seem to require this so lets make it a config option. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable GL 4.5 in compat profileTimothy Arceri2018-08-301-2/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add a thorough clear/copy_buffer benchmarkMarek Olšák2018-08-299-153/+599
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* radeonsi: let internal compute dispatches tune WAVES_PER_SHMarek Olšák2018-08-292-0/+9
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* radeonsi: add TGSI_SEMANTIC_CS_USER_DATA for reading up to 4 SGPRs with TGSIMarek Olšák2018-08-296-3/+34
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* radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SIMarek Olšák2018-08-292-0/+20
| | | | DMA on SI doesn't support the timestamp packet, so it's emulated.
* radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performanceMarek Olšák2018-08-294-2/+51
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