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* radeonsi: rename r600_texture -> si_texture, rxxx -> xxx or sxxxMarek Olšák2018-06-1916-892/+886
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-1958-274/+274
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* freedreno/a5xx: move emit_marker5() into a5xx backendRob Clark2018-06-195-21/+24
| | | | | | | | | The scratch registers move again in a6xx.. so for post-a4xx let's just move this into the backend, and move the one place it used to be needed in core into fd5_emit_ib(). For a6xx we will do similar, calling emit_marker6() from fd6_emit_ib(). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: fix crash in ↵Rob Clark2018-06-193-1/+24
| | | | | | | | | | | dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10 This is kind of a hack, but really the only problem is the debug_assert() in OUT_RELOC(). But the debug_assert() is useful to catch real issues. So just add some #ifdef DEBUG code to filter things out before we hit the assert. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: don't crash if compute shader compile failsRob Clark2018-06-191-0/+2
| | | | | | | It is impolite, and a bit annoying with dEQP (all tests running in single process). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix missing recursion into block conditionRob Clark2018-06-191-0/+4
| | | | | | Fixes a problem seen with dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.row_major_mat4 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: better FOUR_QUAD/TWO_QUAD decision for computeRob Clark2018-06-191-4/+12
| | | | | | If we aren't going to get full occupancy, then use TWO_QUAD. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: bordercolor fixesRob Clark2018-06-191-4/+27
| | | | | | | Need a bit of hand-holding for stencil bordercolor, and add border color values for sRGB. Signed-off-by: Rob Clark <[email protected]>
* freedreno: remove per-stateobj dirty_mask'sRob Clark2018-06-195-37/+16
| | | | | | | | These never got updated in fd_context_all_dirty() so actually trying to rely on them (in the case of fd5_emit_images()) ends up in some cases where state is not emitted but should be. Best to just rip this out. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: remove one image stateblockRob Clark2018-06-191-13/+0
| | | | | | | | I think this ends up just setting uniform/const memory. But we upload x/y/z stride differently. At best this is unneeded, at worst it could possibly clobber other uniform/const memory. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: cubemap image fixesRob Clark2018-06-192-2/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle image bufferRob Clark2018-06-191-1/+8
| | | | | | Similar to txf case, we need to insert a 2nd coordinate (zero). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: handle arrays of imagesRob Clark2018-06-191-6/+30
| | | | | | | | Unlike textures, this doesn't get lowered for us. (Would be nice if they were.. at least until we are ready to deal w/ indirect indexing..) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: images can be arrays tooRob Clark2018-06-192-22/+83
| | | | | | Seems I previously toally forgot about 2d-arrays, etc.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use move_load_const passRob Clark2018-06-191-0/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: ignore PIPE_RESOURCE_FLAG_MAP_COHERENTMarek Olšák2018-06-192-5/+4
| | | | | | | | We treat coherent and non-coherent buffers the same. And move external_usage for better packing. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: always put persistent buffers into GTT on radeonMarek Olšák2018-06-191-1/+5
| | | | | | | This improves performance for certain games. Cc: 18.1 <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: fix si_get_num_queries for radeonMarek Olšák2018-06-191-5/+16
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: don't expose performance counters for non-existent blocksMarek Olšák2018-06-191-13/+16
| | | | Tested-by: Dieter Nützel <[email protected]>
* ac/gpu_info: add radeon_info::num_tcc_blocksMarek Olšák2018-06-191-0/+26
| | | | | | The values for the radeon winsys were copied from the kernel driver. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: set a better NUM_PATCHES hard limitMarek Olšák2018-06-191-3/+10
| | | | | | | | | | AMDVLK uses 64 (distributed) and 16 (non-distributed). radeonsi will use 63 and 16. * This might improve tessellation performance on Hawaii, Bonaire, Tahiti, Pitcairn. (they will use 16) * I'm not sure if this matters for 1 SE configs. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: make sure LS-HS vector lanes are reasonably occupiedMarek Olšák2018-06-191-0/+8
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: properly compute an LS-HS thread group size limitMarek Olšák2018-06-191-2/+3
| | | | | | "64 / max * 4" is less than "64 * 4 / max". Tested-by: Dieter Nützel <[email protected]>
* v3d: Fix blitting from a linear winsys BO.Eric Anholt2018-06-191-0/+36
| | | | | | | | | | | | This is the case for the simulator environment, and broke many blitter tests by trying to texture from linear while the HW can only actually do UIF/UBLINEAR/LT. Just make a temporary and copy into it with the CPU, then blit from that. This is the kind of path that should use the TFU, but I haven't exposed that hardware yet. Fixes dEQP-GLES3.functional.fbo.blit.default_framebuffer.*
* virgl: Remove debugging left-oversTomeu Vizoso2018-06-191-2/+0
| | | | | | | | | | | Some fprintfs were probably left unintentionally a few years ago and are a bit of a nuisance. Fixes: 2d3301e4d513 ("virgl: fix reference counting of prime handles") Cc: Rob Herring <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* mesa/util: add allow_glsl_relaxed_es driconfig overrideTimothy Arceri2018-06-193-0/+4
| | | | | | | | | | | | | | | This relaxes a number of ES shader restrictions allowing shaders to follow more desktop GLSL like rules. This initial implementation relaxes the following: - allows linking ES shaders with desktop shaders - allows mismatching precision qualifiers - always enables standard derivative builtins These relaxations allow Google Earth VR shaders to compile. Reviewed-by: Dave Airlie <[email protected]>
* mesa/util: add allow_glsl_builtin_const_expression driconf overrideTimothy Arceri2018-06-193-0/+4
| | | | | | | Google Earth VR shaders uses builtins in constant expressions with GLSL 1.10. That feature wasn't allowed until GLSL 1.20. Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: enable OpenGL 3.3 compat profileTimothy Arceri2018-06-191-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* v3d: Set the SO offsets correctly if we have to re-emit.Eric Anholt2018-06-185-4/+24
| | | | | | This should fix TF across a glFlush() or TF pause/restart. Fixes dEQP-GLES3.functional.transform_feedback.array.interleaved.lines.highp_float and many, many others.
* gallium/hud: = should rename the last added data sourceMarek Olšák2018-06-181-1/+4
| | | | Tested-by: Dieter Nützel <[email protected]>
* swr/rast: Clang-Format most rasterizer source codeAlok Hota2018-06-18114-22174/+27802
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* mesa: Unconditionally enable floating-point texturesTimothy Arceri2018-06-181-9/+0
| | | | | | | | | | | | | | ARB_texture_float references US Patent #6,650,327 [1] which has a filing date of June 16 1998. According to [2], patents filed after 1995 expire 20 years from the filing date, giving an expiration of June 17 2018. [1] https://www.google.com/patents/US6650327 [2] https://en.wikipedia.org/wiki/Term_of_patent_in_the_United_States Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* v3d: Handle a no-intersection scissor even if it's outside of the VP.Eric Anholt2018-06-151-10/+8
| | | | | | The min/maxes ended up producing a negative clip width/height for dEQP-GLES3.functional.fragment_ops.scissor.outside_render_line. Just make sure they stay at 0 (or v3d 3.x's workaround) if that happens.
* v3d: Use the proper depth texture type for sampling.Eric Anholt2018-06-151-3/+3
| | | | Fixes failing tests in dEQP-GLES3.functional.texture.shadow
* v3d: Fix shaders using pixel center W but no varyings.Eric Anholt2018-06-151-1/+1
| | | | | | | | The docs called this field "uses both center W and centroid W", but actually it's "do you need center W even if varyings don't obviously call for it?" Fixes dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_w
* nvc0: add support for programmable sample locationsRhys Perry2018-06-1410-46/+299
| | | | Signed-off-by: Rhys Perry <[email protected]>
* gallium: add support for programmable sample locationsRhys Perry2018-06-1424-2/+120
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]> (v2) Reviewed-by: Marek Olšák <[email protected]> (v2)
* v3d: Fix polygon offset for Z16 buffers.Eric Anholt2018-06-143-2/+14
| | | | | | Fixes: dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
* v3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.Eric Anholt2018-06-141-1/+2
| | | | | | | | | We need to have the RCL start with EZ enabled, since those undecided draws had EZ enabled. But we do need to update from UNDECIDED to LT or GT as necessary still. Fixes many simulator assertion fails in deqp fragment_ops/interaction/basic_shader/*
* v3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.Eric Anholt2018-06-141-2/+2
| | | | This doesn't really matter, since they both get rounded up to 4096.
* v3d: Add static asserts for other packed packet sizes.Eric Anholt2018-06-142-0/+7
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* v3d: Fix the size of the packed attribute state.Eric Anholt2018-06-141-1/+1
| | | | Fixes segfaults in dEQP-GLES3.functional.vertex_array_objects.all_attributes.
* v3d: Remove some unused context fields from vc4.Eric Anholt2018-06-141-11/+0
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* v3d: Remove unused QUNIFORM_STENCIL left over from vc4.Eric Anholt2018-06-141-9/+0
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* v3d: Use our #define for max attributes in shader caps.Eric Anholt2018-06-141-1/+1
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* meson: only build vl_winsys_dri.c when x11 platform is usedLukas Rusak2018-06-141-1/+1
| | | | | | | | | | | | | | This seems to have been missed in the move from autotools This fixes the following build issue: ../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory #include <X11/Xlib-xcb.h> ^~~~~~~~~~~~~~~~ Fixes: b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e ("meson: Build gallium auxiliary") Reviewed-by: Dylan Baker <[email protected]>
* radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointersMarek Olšák2018-06-131-2/+2
| | | | | | | | This fixes: GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations Cc: 18.0 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi/gfx9: update & clean up a DPBB heuristicMarek Olšák2018-06-131-9/+5
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bugMarek Olšák2018-06-131-2/+4
| | | | | | This may not be needed yet, but let's set it now. Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: remove UINT_MAX array terminators in bin size tablesMarek Olšák2018-06-131-19/+1
| | | | Tested-by: Dieter Nützel <[email protected]>
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