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* nv50: fix alphatest for non-blendable formatsIlia Mirkin2016-07-1614-11/+118
| | | | | | | | | | | | | | | | | | | | The hardware can only do alphatest when using a blendable format. This means that the various *16 norm formats didn't work with alphatest. It appears that Talos Principle uses such formats, as well as alpha tests, for some internal renders, which made them be incorrect. However this does not appear to affect the final renders, but in a different game it easily could. The approach we take is that when alphatests are enabled and a suitable format is used (which we anticipate is the vast minority of the time), we insert code into the shader to perform the comparison and discard. Once inserted, that code lives in the shader forever, and we re-upload it each time the function changes with a fixed-up compare. To avoid re-uploading too often, if we switch back to a blendable format, the test is (effectively) disabled and the hw alphatest functionality is used. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/u_queue: add optional cleanup callbackRob Clark2016-07-165-5/+14
| | | | | | | | | | | | Adds a second optional cleanup callback, called after the fence is signaled. This is needed if, for example, the queue has the last reference to the object that embeds the util_queue_fence. In this case we cannot drop the ref in the main callback, since that would result in the fence being destroyed before it is signaled. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove the DRAW_PREAMBLE packetNicolai Hähnle2016-07-163-12/+1
| | | | | | | According to firmware guys, the new sequence that we added for Polaris should work on all CIK parts, and should actually be faster on some parts. Reviewed-by: Marek Olšák <[email protected]>
* vc4: Speed up glGenerateMipmaps by avoiding shadow baselevel.Eric Anholt2016-07-155-3/+23
| | | | | | | | | | | | | To support general GL_TEXTURE_BASE_LEVEL we have to copy to a temporary miptree. However, if a single level is being selected, we can use the existing miptree and force all the sampling to be from that particular level. This avoids a ton of software fallbacks in glGenerateMipmaps(), which uses base levels in the blit implementation in gallium. Improves "glmark2 -b terrain" from 2 fps to 3 (perhaps some more precision would be useful?), and cuts its CPU usage during the benchmarking from ~30% to ~10% (total CPU time from 8.8s to 7.6s).
* vc4: Drop VC4_DIRTY_TEXSTATE in favor of the per-stage flags.Eric Anholt2016-07-154-8/+4
| | | | | | The compiler uses the per-stage flags already, so it didn't need this. vc4_uniforms was using it, so just replace it with both of the stage flags for now.
* vc4: Remove dead dirty_samplers field.Eric Anholt2016-07-152-5/+0
| | | | We use a big VC4_DIRTY_FRAGTEX/VC4_DIRTY_VERTEX on the stage, instead.
* vc4: Turn on control flow support in the simulator environment.Eric Anholt2016-07-151-0/+4
| | | | | We can't merge the non-simulator support until we merge the kernel side and get a new libdrm release.
* svga: avoid ubinding render targets that have already been unboundCharmaine Lee2016-07-151-1/+6
| | | | | | | | Fixed the remaining redundant SetRenderTargets command emission. Tested with lightsMark2008, Heaven, mtt piglit, glretrace, conform. Reviewed-by: Brian Paul <[email protected]>
* svga: dump code for GenMips.Neha Bhende2016-07-151-0/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* Use correct names for dlopen()ed files on CygwinYaakov Selkowitz2016-07-151-0/+2
| | | | | Signed-off-by: Yaakov Selkowitz <[email protected]> Reviewed-by: Jon Turney <[email protected]>
* svga: handle mismatched number of samplers, sampler viewsBrian Paul2016-07-151-5/+10
| | | | | | | | | | | | | in svga_init_shader_key_common(). Since the CSO module only tracks sampler views for fragment shaders, the number of samplers and sampler views can be mismatched for other types of shaders. This situation triggered an assertion in Chrome with maps.google.com This patch adds defensive code to handle that situation. Fixes VMware bug 1694027 Cc: <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* st/omx/enc: check uninitialized list from task releaseLeo Liu2016-07-151-2/+2
| | | | | | | | | The uninitialized list should be checked and returned. Thank Julien for the notification and suggested fix. Signed-off-by: Leo Liu <[email protected]> Cc: "12.0" <[email protected]>
* nv50/ir: add missing string for SV_WORK_DIMSamuel Pitoiset2016-07-141-0/+1
| | | | | | | Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Hans de Goede <[email protected]>
* Revert "radeon/llvm: Use alloca instructions for larger arrays"Marek Olšák2016-07-142-149/+25
| | | | | | This reverts commit 513fccdfb68e6a71180e21827f071617c93fd09b. Bioshock Infinite hangs with that.
* r600,compute: Reserve vtx 3 for kernel argumentsJan Vesely2016-07-141-3/+7
| | | | | | | | | Using vtx 0 does not work for dynamic offsets. v2: add explanatory comment Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission failsMarek Olšák2016-07-141-6/+9
| | | | | | This is the bare minimum for reporting the error to the user. Reviewed-by: Christian König <[email protected]>
* winsys/amdgpu: return an error on IB submission failuresMarek Olšák2016-07-142-1/+9
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/radeon: add a return value to cs_flushMarek Olšák2016-07-143-9/+13
| | | | | | Required by our UVD code. Reviewed-by: Christian König <[email protected]>
* freedreno/a4xx: Fix sign compare warnings[email protected]2016-07-141-7/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: Fix sign compare warnings[email protected]2016-07-141-7/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: Fix sign compare warnings[email protected]2016-07-141-4/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeon/vce: handle newly added parametersBoyuan Zhang2016-07-141-13/+20
| | | | | | | Replace the previous hardcoded value with newly defined parameters Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx: assign previous values to new structureBoyuan Zhang2016-07-141-0/+10
| | | | | | | | Assign previously hardcoded values for OMX to newly defined structure. As a result, OMX behaviour will not change at all. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: add parameters for VAAPI encodeBoyuan Zhang2016-07-141-0/+33
| | | | | | | | Allow to specify more parameters in the encoding interface which previously just hardcoded in the encoder Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* vc4: Emit resets of the uniform stream at the starts of blocks.Eric Anholt2016-07-139-0/+167
| | | | | | | | If a block might be entered from multiple locations, then the uniform stream will (probably) be at different points, and we need to make sure that it's pointing where we expect it to be. The kernel also enforces that any block reading a uniform resets uniforms, to prevent reading outside of the uniform stream by using looping.
* vc4: Add support for scheduling of branch instructions.Eric Anholt2016-07-132-17/+114
| | | | For now we don't fill the delay slots, and instead just drop in NOPs.
* vc4: Move the QPU instructions to schedule into each block.Eric Anholt2016-07-134-141/+180
| | | | We'll want to schedule them individually, to handle delay slots.
* vc4: Disable vc4_opt_vpm in the presence of control flow.Eric Anholt2016-07-131-0/+5
| | | | | | It's a really valuable pass currently, but it will be a mess to rewrite for control flow. For now, just disable it if we have multiple blocks present.
* vc4: Convert vc4_opt_dead_code to work in the presence of control flow.Eric Anholt2016-07-131-18/+29
| | | | | | | | | | | | With control flow, we can't be sure that we'll see the uses of a variable before its def as we walk backwards. Given that NIR is eliminating our long chains of dead code, a simple solution for now seems fine. This slightly changes the order of some optimizations, and so an opt_vpm happens before opt_dce, causing 3 dead MOVs to be turned into dead FMAXes in Minecraft: instructions in affected programs: 52 -> 54 (3.85%)
* vc4: Update copy propagation for control flow.Eric Anholt2016-07-131-62/+137
| | | | | | | | | | | | | | Previously, we could assume that a MOV from a temp was always an available copy, because all temps were SSA in NIR, and their non-SSA state in QIR was just due to the fact that they were from a bcsel or pack_unorm_4x8, so we could use the current value of the temp after that series of QIR instructions to define it. However, this is no longer the case with control flow. Instead, we track a new array of MOVs defined within the block that haven't had their source or dest killed yet, and use that primarily. We fall back to looking through the QIR defs array to handle across-block MOVs, but now require that copies from the SSA defs have an SSA src as well.
* Revert "gallium: Force blend color to 16-byte alignment"Tim Rowley2016-07-131-11/+1
| | | | | | | | | | | | | | This reverts commit d8d6091a846ac2a40a011d512d6d57f6c8442e6a. Heap allocations may be only 8-byte aligned on 32-bit system, and so having members with 16-byte alignment (such as in the case where pipe_blend_color is embedded in radeonsi's si_context) is undefined behavior which indeed causes crashes when compiled with gcc -O3. Cc: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96835 Signed-off-by: Tim Rowley <[email protected]> Acked-by: Chuck Atkins <[email protected]>
* radeonsi: report accurate SGPR and VGPR spillsMarek Olšák2016-07-132-5/+15
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for a compute VGPR-usage LLVM bugMarek Olšák2016-07-131-0/+35
| | | | | | | v2: use abort(), describe which LLVM version is affected Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use LLVMGetTypeKind to tell if an input is an array of descriptorsMarek Olšák2016-07-131-19/+11
| | | | | | just a cleanup Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: replace !tbaa with !invariant.loadMarek Olšák2016-07-131-12/+5
| | | | | | no change in generated code thanks to dereferenceable(n) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set dereferenceable attribute on descriptor arraysMarek Olšák2016-07-131-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows moving the loads arbitrarily in the Sinking pass. 26002 shaders in 14643 tests Totals: SGPRS: 2080160 -> 2080160 (0.00 %) VGPRS: 798875 -> 797826 (-0.13 %) Spilled SGPRs: 108485 -> 79165 (-27.03 %) Spilled VGPRs: 327 -> 327 (0.00 %) Scratch VGPRs: 1656 -> 1652 (-0.24 %) dwords per thread Code Size: 36127192 -> 35559780 (-1.57 %) bytes LDS: 767 -> 767 (0.00 %) blocks Max Waves: 212464 -> 212672 (0.10 %) Wait states: 0 -> 0 (0.00 %) PERCENTAGES / App Shaders SGPRs VGPRs SpillSGPR SpillVGPR Scratch CodeSize MaxWaves Waits (unknown) 4 . . . . . . . . 0ad 6 . . . . . . . . alien_isolation 2938 . 0.04 % -8.53 % . . -0.71 % -0.06 % . anholt 10 . . . . . . . . batman_arkham_origins 589 . -0.58 % -79.54 % . . -6.72 % 0.57 % . bioshock-infinite 1769 . -0.65 % -89.32 % . . -4.73 % 0.48 % . borderlands2 3968 . -0.31 % -51.21 % . . -4.09 % 0.22 % . brutal-legend 338 . -0.03 % -2.95 % . . -0.06 % . . civilization_beyond.. 116 . . -14.17 % . . -0.88 % . . counter_strike_glob.. 1142 . . . . . . . . dirt-showdown 541 . -0.56 % -40.14 % . -3.45 % -1.82 % 0.35 % . dolphin 22 . . . . . 0.16 % . . dota2 1747 . . . . . 0.01 % . . europa_universalis_4 76 . -0.23 % -42.11 % . . -0.96 % . . f1-2015 774 . -0.09 % -28.89 % . . -2.60 % 0.09 % . furmark-0.7.0 4 . . . . . . . . gimark-0.7.0 10 . . . . . . . . glamor 16 . . . . . . . . humus-celshading 4 . . . . . . . . humus-domino 6 . . . . . . . . humus-dynamicbranching 24 . 0.71 % . . . 0.29 % -0.45 % . humus-hdr 10 . . . . . . . . humus-portals 2 . . . . . . . . humus-volumetricfog.. 6 . . . . . . . . left_4_dead_2 1762 . . . . . . . . metro_2033_redux 2670 . -0.10 % -7.15 % . . -0.03 % . . nexuiz 80 . . . . . . . . pixmark-julia-fp32 2 . . . . . . . . pixmark-julia-fp64 2 . . . . . . . . pixmark-piano-0.7.0 2 . . . . . . . . pixmark-volplosion-.. 2 . . . . . . . . plot3d-0.7.0 8 . . . . . . . . portal 474 . . . . . . . . sauerbraten 7 . . . . . . . . serious_sam_3_bfe 392 . . -13.20 % . . -1.81 % . . supertuxkart 4 . . . . . . . . talos_principle 324 . -0.21 % -18.39 % . . -2.73 % 0.14 % . team_fortress_2 808 . . . . . . . . tesseract 430 . 0.08 % -68.57 % . . -0.45 % . . tessmark-0.7.0 6 . . . . . . . . thea 172 . . . . . 0.03 % . . ue4_effects_cave 299 . -0.04 % -10.15 % . . -0.25 % 0.04 % . ue4_elemental 586 . -0.02 % -13.93 % . . -0.13 % 0.02 % . ue4_lightroom_inter.. 74 . -0.17 % -70.00 % . . -1.27 % . . ue4_realistic_rende.. 92 . . -32.58 % . . -0.35 % . . unigine_heaven 322 . 0.12 % -54.17 % . . -1.42 % -0.12 % . unigine_sanctuary 264 . . . . . . . . unigine_tropics 210 . . . . . . . . unigine_valley 278 . -0.15 % -40.74 % . . -2.00 % 0.09 % . unity 72 . . . . . 0.03 % . . warsow 176 . . . . . . . . warzone2100 4 . . . . . 0.13 % . . witcher2 1040 . -0.03 % -86.28 % . . -0.28 % 0.01 % . xcom_enemy_within 1236 . -0.24 % -63.54 % . . -0.93 % 0.18 % . yofrankie 82 . -0.61 % -100.00 % . . -0.83 % 0.41 % . ----------------------------------------------------------------------------------------------------------- Total 26002 . -0.13 % -27.03 % . -0.24 % -1.57 % 0.10 % . Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: add helper lp_add_attr_dereferenceableMarek Olšák2016-07-132-0/+14
| | | | | | | | | Not sure if this is the right way to do it, but it seems to work. v2: make it a no-op on LLVM <= 3.5 Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up shader value metadata codeMarek Olšák2016-07-131-15/+19
| | | | | | | No change in behavior. BTW, tbaa_md_kind == 1, which was the magic number in the code. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove LLVMNoUnwindAttribute usesMarek Olšák2016-07-131-36/+31
| | | | | | always set by gallivm Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a typo in SI_PARAM_LINEAR_* handlingMarek Olšák2016-07-131-1/+1
| | | | | | introduced in 476e9cee1d0cbe321c401277214e6c36ce5b18c9 Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: normalize the code styleMarek Olšák2016-07-132-338/+286
| | | | | | no change in behavior Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: just save buffer sizes instead of buffers while recording IBsMarek Olšák2016-07-135-10/+5
| | | | | | whole buffer objects are not needed Reviewed-by: Nicolai Hähnle <[email protected]>
* Add c99_alloca.h include to fix compilation on CygwinJon Turney2016-07-131-0/+1
| | | | | | | | Fix compilation on Cygwin, since 50b22354, by adding c99_alloca.h include, which should know how to portably make the alloc() prototype available. Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: silence Coverity warningNicolai Hähnle2016-07-132-0/+4
| | | | | | | | Coverity's analysis is too weak to understand that r600_init_flushed_depth(_, _, NULL) only returns true when flushed_depth_texture was assigned a non-NULL value. Reviewed-by: Marek Olšák <[email protected]>
* vc4: Validate QPU uniform pointer updates.Eric Anholt2016-07-121-0/+22
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* vc4: Add support for NIR loops and break/continue.Eric Anholt2016-07-122-3/+79
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* vc4: Add support for emitting NIR IF nodes.Eric Anholt2016-07-121-1/+91
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* vc4: Add support for storing to NIR registers in a non-SSA fashion.Eric Anholt2016-07-122-85/+144
| | | | | | | Previously, there were occasionally NIR registers in our programs, but they were always actually used SSA-only. Now that we're trying to support control flow, we need to actually conditionally move to registers based on whether channels are active or not.
* vc4: Add a flag in the screen to track control flow support.Eric Anholt2016-07-123-1/+14
| | | | | For now it's still always false, but I need it in place for kernel backwards compat support as I extend the backend for control flow.
* vc4: Define a QIR branch instructionEric Anholt2016-07-124-9/+61
| | | | | | This uses the branch condition code in inst->cond to jump to either successor[0] (condition matches) or successor[0] (condition doesn't match).
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 21:43:48 +0000