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* build: Stop using GALLIUM_STATE_TRACKERS_DIRS for SUBDIRSMatt Turner2013-04-151-11/+54
| | | | | | | | configure still uses it to print the enabled state trackers. Tested-by: Emil Velikov <[email protected]> Reviewed-and-Tested-by: Andreas Boll <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* build: Remove GALLIUM_DIRSMatt Turner2013-04-151-22/+0
| | | | | | | | It's always constant anyway. Tested-by: Emil Velikov <[email protected]> Reviewed-and-Tested-by: Andreas Boll <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* build: Move src/mapi/mapi/* to src/mapi/Matt Turner2013-04-153-4/+4
| | | | | | Tested-by: Emil Velikov <[email protected]> Reviewed-and-Tested-by: Andreas Boll <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* radeonsi: Read config values from the .AMDGPU.config ELF sectionTom Stellard2013-04-152-8/+28
| | | | | | | | | Instead of emitting configuration values (e.g. number of gprs used) in a predefined order, the LLVM backend now emits these values in register/value pairs. The first dword contains the register address and the second dword contians the value to write. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: Handle ELF formatted binary output from the LLVM backendTom Stellard2013-04-153-6/+37
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* radeon/llvm: Use a struct for storing compiled codeTom Stellard2013-04-154-28/+38
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* gallivm: fix small but severe bug in handling multiple lod level stridesRoland Scheidegger2013-04-151-1/+1
| | | | | | | | | | | | | | | | | Inserting the value for the second quad in the wrong place for the following shuffle. This meant the row or image stride was undefined which is quite catastrophic, can lead to bogus texels fetched or just segfault. This code is only hit for SoA path currently, still surprising it didn't crash more or caused more visible issues (I think llvm used a broadcast shuffle for the undefined parts of the vector, hence the undefined value for the second quad was just the same as that from the first quad, so as long as both quads hit the same mip level everything was fine, and since lower mips always have the same large stride it made it less likely to hit out-of-bound memory in case of differing lods). Note: this is a candidate for stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* clover: Fix usage of incorrect object as destination in ↵Francisco Jerez2013-04-131-1/+1
| | | | | | clEnqueueCopyBufferToImage. Signed-off-by: Francisco Jerez <[email protected]>
* clover: Define platform class and merge with device_registry.Francisco Jerez2013-04-138-68/+155
| | | | | | | | | | | | | Null platform IDs are OK according to the spec, but some applications have been reported to get paranoid and assume that our NULL platform is unusable. As it doesn't hurt to have device enumeration separate from the rest of the device code (quite the opposite, it makes the code cleaner), make the API use an actual platform object that keeps track of the available devices instead of the former NULL pointer. Reported-and-reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Francisco Jerez <[email protected]>
* clover: Add missing fields to the module serializer.Francisco Jerez2013-04-131-0/+2
| | | | Signed-off-by: Francisco Jerez <[email protected]>
* r300g: Fix bug in OMOD optimizationTom Stellard2013-04-121-1/+3
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=60503 NOTE: This is a candidate for the stable branches.
* nvc0: set ret variable if launch desc allocation failedEmil Velikov2013-04-121-1/+3
| | | | | | | | | | | | | | | Pointed out by gcc nve4_compute.c: In function 'nve4_launch_grid': nve4_compute.c:511:7: warning: 'ret' may be used uninitialized in this function [-Wmaybe-uninitialized] if (ret) ^ Signed-off-by: Emil Velikov <[email protected]> Edit by Christoph Bumiller: Set it to -1 to indicate failure and only when it's actually required.
* nvc0: bail out early during nve4_compute_setup()Emil Velikov2013-04-121-1/+1
| | | | | | | Exit gracefully rather than trying to create a random object, whenever the chipset is unknown Signed-off-by: Emil Velikov <[email protected]>
* nvc0: compile nve4_cache_split_name() only in debug buildEmil Velikov2013-04-121-1/+1
| | | | | | | | | | As otherwise it is unused - pointed out by gcc nve4_compute.c:586:20: warning: 'nve4_cache_split_name' defined but not used [-Wunused-function] static const char *nve4_cache_split_name(unsigned value) ^ Signed-off-by: Emil Velikov <[email protected]>
* nv50/codegen: do not emitATOM() if the subOp is unknownEmil Velikov2013-04-121-1/+1
| | | | | | | | | | | | For debug build we'll hit the assert, for release we are going to emit random data as subOp is used uninitilised. Spotted by gcc codegen/nv50_ir_emit_nv50.cpp: In member function 'void nv50_ir::CodeEmitterNV50::emitATOM(const nv50_ir::Instruction*)': codegen/nv50_ir_emit_nv50.cpp:1554:12: warning: 'subOp' may be used uninitialized in this function [-Wmaybe-uninitialized] uint8_t subOp; ^ Signed-off-by: Emil Velikov <[email protected]>
* nvc0: implement multisample texturesChristoph Bumiller2013-04-1210-25/+97
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* nvc0: patch up TEX cases with 5 or 6 sources on nve4Christoph Bumiller2013-04-121-1/+19
| | | | Hackishly fixes alignment requirement of 2nd tuple for now.
* nvc0: fix 2D engine MS2 resolveChristoph Bumiller2013-04-121-2/+2
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* nv50,nvc0: add RGBX16/32_FLOAT formatsChristoph Bumiller2013-04-121-0/+4
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* r600g: add get_sample_position support (v3)Dave Airlie2013-04-112-122/+240
| | | | | | | v2: I rewrote this to use the sample positions properly. v3: rewrite properly to use bitfield to cast back to signed ints Signed-off-by: Dave Airlie <[email protected]>
* gallium: add get_sample_position interfaceDave Airlie2013-04-111-0/+13
| | | | | | | This is to be used to implement glGet GL_SAMPLE_POSITION. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix two issues in compressed msaa reading codeDave Airlie2013-04-111-2/+2
| | | | | | | | | I've no idea when sample_chan would ever be 4 here, but 4 is most definitely wrong, array textures have it as 3 as well. Also the cayman code though unused is obviously wrong. Signed-off-by: Dave Airlie <[email protected]>
* radeon/uvd: add UVD implementation v5Christian König2013-04-1115-21/+1924
| | | | | | | | | | | | | | Just everything you need for UVD with r600g and radeonsi. v2: move UVD code to radeon subdir, clean up build system additions, remove an unused SI function, disable tiling on SI for now. v3: some minor indentation fix and rebased v4: dpb size calculation fixed v5: implement proper fall-back in case the kernel doesn't support UVD, based on patches from Andreas Boll but cleaned up a bit more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/winsys: add uvd ring support to winsys v3Christian König2013-04-113-0/+31
| | | | | | | | | | | | | Separated from UVD patch for clarity. v2: sync with next tree for 3.10 v3: as pointed out by Andreas Bool check for drm minor >= 32 http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.10-wip Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Andreas Boll <[email protected]>
* r600g: Add support for GL_ARB_texture_buffer_rangeFredrik Höglund2013-04-113-5/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix valgrind warning on CaymanMarek Olšák2013-04-101-1/+1
| | | | Warning: "Conditional jump or move depends on uninitialised value(s)".
* gallivm/tgsi: handle untyped movesZack Rusin2013-04-102-0/+10
| | | | | | | | | | | both mov and ucmp can be used to move variables of any type. correctly note that about ucmp in the tgsi_info and make sure gallivm can handle that by correctly casting the untyped moves. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix loops and conditionals within GSZack Rusin2013-04-102-19/+105
| | | | | | | | | | | | | We were using simple temporaries, without using alloca or phi nodes which meant that on every iteration of the loop our temporaries, which were holding the number of vertices and primitives which were emitted, were being reset to zero. Now we're using alloca to allocate those variables to preserve them across conditionals. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: implement PIPE_QUERY_SO_STATISTICSZack Rusin2013-04-102-0/+21
| | | | | | | | | | We were missing the implementation of PIPE_QUERY_SO_STATISTICS query, this change implements it on top of the existing facilities. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix unsigned divide and remainder opcodesZack Rusin2013-04-101-4/+33
| | | | | | | | | | We want to both make sure we never divide by zero to not generate sigfpe and that divide by zero is guaranteed to return 0xffffffff. Based on José idea. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: fix breakcZack Rusin2013-04-101-12/+14
| | | | | | | | | we break when the mask values are 0 not, 1, plus it's bit comparison not a floating point comparison. This fixes both. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: remove sampler writemask v3Christian König2013-04-102-13/+8
| | | | | | | | v2: fix instrinsic name as well v3: LLVM revision incremented as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* pipe-loader: Fix out of source buildNiels Ole Salscheider2013-04-101-2/+2
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* st/osmesa: re-use buffers in OSMesaMakeCurrent()Brian Paul2013-04-091-7/+54
| | | | | | | Rather than creating a new buffer each time. Fixes problems found with vtk. Tested-by: Kevin H. Hobbs <[email protected]>
* st/vdpau: fix subtitle related bug v2Christian König2013-04-091-0/+4
| | | | | | | | | | Drawing subtitles didn't increased the dirty area of the surface. Reported and tested by freeedrich on irc. v2: don't clear the surface Signed-off-by: Christian König <[email protected]>
* softpipe: misc updates to image dumping in softpipe_flush()Brian Paul2013-04-091-3/+4
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* tgsi: Ensure struct tgsi_ind_register field Index is initialized.Vinson Lee2013-04-081-0/+1
| | | | | | | Fixes uninitialized scalar variable defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g: Fix UMAD on CaymanMartin Andersson2013-04-091-13/+32
| | | | | | | | | | | | The multiplication part of tgsi_umad did not work on Cayman, because it did not populate the correct vector slots. This fixed hardlocks in the EXT_transform_feedback/order tests. NOTE: This is a candidate for the stable branches. (might not be easy to cherry-pick though) Signed-off-by: Marek Olšák <[email protected]>
* r600g/llvm: Add support for native isa for pre EGVincent Lejeune2013-04-082-2/+6
| | | | | This fixes bug 62756 : https://bugs.freedesktop.org/show_bug.cgi?id=62756#c12
* gallium/util: add const to a parameter of util_max_layerMarek Olšák2013-04-061-1/+1
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* radeonsi: Add compute support v3Tom Stellard2013-04-0511-49/+378
| | | | | | | | | | | v2: - Only dump shaders when env variable is set. v3: - Don't emit VGT registers Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]
* radeonsi: Set TCL1_ACTION_ENA when invalidating the texture cacheTom Stellard2013-04-051-0/+1
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]
* radeonsi: Remove si_pm4_inval_vertex_cache()Tom Stellard2013-04-053-8/+1
| | | | | | | | This function is a holdover from r600g and is identical to si_pm4_inval_texture_cache(), so it is not needed. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]
* gallium: PIPE_COMPUTE_CAP_IR_TARGET - allow drivers to specify a processor v2Tom Stellard2013-04-0510-80/+105
| | | | | | | | | | | | This target string now contains four values instead of three. The old processor field (which was really being interpreted as arch) has been split into two fields: processor and arch. This allows drivers to pass a more a more detailed description of the hardware to compiler frontends. v2: - Adapt to libclc changes Reviewed-by: Francisco Jerez <[email protected]>
* util: add ETC as compressed formatWladimir2013-04-051-0/+1
| | | | | | | Add UTIL_FORMAT_LAYOUT_ETC to util_format_is_compressed. It was missing. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: fix is_blit_generic_supported() stencil checkingBrian Paul2013-04-051-12/+14
| | | | | | | | | | | | | | | Don't check if there's sampler support for stencil if we're not going to actually blit/copy stencil values. Fixes the case where we mistakenly said we can't support a blit of depth values from S8Z24 to X8Z24. Also, rename the is_stencil variable to dst_has_stencil to improve readability. NOTE: This is a candidate for the stable branches. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* freedreno: use autogenerated register defsRob Clark2013-04-0523-1617/+2116
| | | | | | | | | | | | | Switch to use the envytools generated headers for register/bitfield definitions. This is the first step in preparing to add a3xx support, since it avoids having conflicting names for a3xx and a2xx registers. And since I'm using envytools for a3xx it is simpler to just use it for everything. This shouldn't cause any functional change, it is really just a lot of renaming. Signed-off-by: Rob Clark <[email protected]>
* st/wgl: Install our windows message hook to threads created before the ICD ↵José Fonseca2013-04-052-26/+196
| | | | | | | | | | | | | | | is loaded. Otherwise we will not receive destroy windows events, causing framebuffers to leak. This happens particularly with java and jogl. Tested with java + jogl, MATLAB. VMware Internal Bug Number: 1013086. Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: Work without sse2 if llvm is new enoughAdam Jackson2013-04-051-2/+3
| | | | | | | | At least on llvm 3.2 this appears to work fine. Tested on an Athlon XP 2600+, which has sse and 3dnow but not sse2. Reviewed-by: Jose Fonseca <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* winsys/radeon: add command stream replay dump for faulty lockup v3Jerome Glisse2013-04-057-37/+443
| | | | | | | | | | | | | | | | | | Build time option, set RADEON_CS_DUMP_ON_LOCKUP to 1 in radeon_drm_cs.h to enable it. When enabled after each cs submission the code will try to detect lockup by waiting on one of the buffer of the cs to become idle, after a timeout it will consider that the cs triggered a lockup and will write a radeon_lockup.c file in current directory that have all information for replaying the cs. To build this file : gcc -O0 -g radeon_lockup.c -ldrm -o radeon_lockup -I/usr/include/libdrm v2: Add radeon_ctx.h file to mesa git tree v3: Slightly improve dumped file for easier editing, only dump first faulty cs Signed-off-by: Jerome Glisse <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 23:52:50 +0000