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* softpipe: use the polygon stipple utility moduleBrian Paul2011-07-219-14/+131
| | | | | | | | | | This is an alternative to the draw module's polygon stipple stage. The softpipe implementation here is just a test. The advantange of using the new polygon stipple utility module (with other drivers) is we can avoid software vertex processing in the draw module and get much better performance. Polygon stipple doesn't require special vertex processing like the other draw module stage.
* softpipe: implement fragment shader variantsBrian Paul2011-07-2113-117/+251
| | | | We'll need shader variants to accomodate the new polygon stipple utility.
* util: assorted updates to polygon stipple helperBrian Paul2011-07-211-10/+33
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* softpipe: use tgsi_shader_info fields for fragcoord origin, center, etc.Brian Paul2011-07-214-17/+5
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* tgsi: add info fields for fragcoord origin, center, etcBrian Paul2011-07-212-10/+31
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* softpipe: remove obsolete commentBrian Paul2011-07-211-4/+0
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* softpipe: rename a functionBrian Paul2011-07-211-7/+7
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* svga: fix typos, update commentsBrian Paul2011-06-081-7/+5
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* st/egl: set EGL_ALPHA_MASK_SIZEChia-I Wu2011-06-091-0/+4
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* r600g: fix mixup in GPR resource reg setupAlex Deucher2011-06-081-3/+10
| | | | | | | GLOBAL_GPR regs should be 0. Need to set the number of temp regs in SQ_GPR_RESOURCE_MGMT_1. Signed-off-by: Alex Deucher <[email protected]>
* gallium: fix comments for pipe_stream_output_stateBrian Paul2011-06-081-7/+9
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* gallium: s/bool/boolean/Brian Paul2011-06-0813-21/+21
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* draw: fix edge flag handling in clipper (for unfilled tris/quads/polygons)Brian Paul2011-06-081-5/+57
| | | | | | | | | | | | | | | | | | | | Previously, we were errantly drawing some interior edges of clipped polygons and quads. Also, we were introducing extra edges where polygons intersected the view frustum clip planes. The main problem was that we were ignoring the edgeflags encoded in the primitive header's 'flags' field which are set during polygon/quad ->tri decomposition. We need to observe those during clipping. Since we can't modify the existing vert's edgeflag fields, we need to store them in a parallel array. Edge flags also need to be handled differently for view frustum planes vs. user-defined clip planes. In the former case we don't want to draw new clip edges but in the later case we do. This matches NVIDIA's behaviour and it just looks right. Finally, note that the LLVM draw code does not properly set vertex edge flags. It's OK on the regular software path though.
* r600g: missed one line in eg dyn gpr fallback.Dave Airlie2011-06-081-0/+1
| | | | | | need more sleep or something. Signed-off-by: Dave Airlie <[email protected]>
* r600g: set enable always bits for r600/r700 sq registers.Dave Airlie2011-06-081-11/+11
| | | | | | This makes sure these are enabled even if set to 0 at startup. Signed-off-by: Dave Airlie <[email protected]>
* r600g: condition evergreen dyn gpr resource managementDave Airlie2011-06-082-2/+33
| | | | | | | So only with kernel version 2.7 can this work, thanks to Alex for pointing that out. Also add a workaround for a hw bug. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix warnings in winsys.Dave Airlie2011-06-081-5/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable dynamic GPR resource management on evergreenDave Airlie2011-06-083-20/+11
| | | | | | | | | | | Evergreen can do this as well as cayman, so we should enable it. This fixes a gpu lockup with glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined.shader_test I need to add a better workaround for r600/r700. Signed-off-by: Dave Airlie <[email protected]>
* r600g: only add blocks once to the dirty/enabled lists.Dave Airlie2011-06-081-3/+5
| | | | | | This caused a loop in some tests. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix regression in recent state changes.Dave Airlie2011-06-081-0/+1
| | | | | | | | | | We weren't emitting the SQ setup regs at all which really is fail. When a state is always enabled we need to add it to the dirty list as well. Signed-off-by: Dave Airlie <[email protected]>
* r600g: move simple part of bo reloc processing inline.Dave Airlie2011-06-082-12/+17
| | | | | | | This just moves the messy stuff out of the fast path, and leaves the fast-case in the fast path. Signed-off-by: Dave Airlie <[email protected]>
* r600g: take alpha ref update out of line.Dave Airlie2011-06-081-5/+4
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: split resource emit path from main register emit pathDave Airlie2011-06-084-17/+106
| | | | | | | | | Since resources don't generally vary in size, this splits the emit path, it also takes into a/c that texture and vertex resources have different number of relocs, and avoids emitting the extra reloc for vertex resources. Signed-off-by: Dave Airlie <[email protected]>
* r600g: exit bo per reg scanning loop early.Dave Airlie2011-06-082-9/+13
| | | | | | | | | Exit this loop early to avoid pointless iterations later. Move the resource bos to the first two regs, it actually doesn't matter which regs we use for this in resource land. Signed-off-by: Dave Airlie <[email protected]>
* r600g: reorder evergreen draw packets to be smaller.Dave Airlie2011-06-081-4/+8
| | | | | | | We were always re-emitting lots of unnecessary changes here, avoid doing that. Signed-off-by: Dave Airlie <[email protected]>
* r600g: inline r600_bo_reference.Dave Airlie2011-06-083-13/+15
| | | | | | This relies on the reference member being first, so document it. Signed-off-by: Dave Airlie <[email protected]>
* r600g: no need to drop the references here.Dave Airlie2011-06-081-2/+0
| | | | | | We drop them when we reference the new objects in the next line. Signed-off-by: Dave Airlie <[email protected]>
* r600g: use memcmp instead of a loop in state_set_resourceDave Airlie2011-06-081-5/+3
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g : fix incorrect size computation in r600_query_resultPierre-Eric Pelloux-Prayer2011-06-071-1/+2
| | | | | | | | | | | | | query->num_results already has the size in dwords of the query buffer. There no need to multiply again. We were reading past the end of the buffer, resulting in reading garbage. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37028 agd5f: clarify the comment. Signed-off-by: Alex Deucher <[email protected]>
* r600g: remove pre-r6xx asic families and pci idsAlex Deucher2011-06-072-35/+0
| | | | | | Not sure why these were included originally. Signed-off-by: Alex Deucher <[email protected]>
* r600g: always clear query memoryAlex Deucher2011-06-071-3/+3
| | | | | | | | | | | | | According to the hw documentation, the driver needs to: - allocate 128 bits for each possible DB - clear the 128 bits for each possible DB - write 1 to bits 127 and 63 for upper DBs that don't exist on a particular asic Previously we were only doing these steps if the asic had less than the max possible DBs. Signed-off-by: Alex Deucher <[email protected]>
* r300g: consolidate deducing chipset infoMarek Olšák2011-06-074-392/+107
| | | | Use the new PCI ID table, make it simpler.
* r600g: add missing r300 familiesMarek Olšák2011-06-071-0/+5
| | | | Wondering why r600g needs to include r300_pci_ids.h
* r300g: Remove is_r3xxBenjamin Franzke2011-06-073-215/+9
| | | | | | Use r300_pci_ids.h instead. Reviewed-by: Alex Deucher <[email protected]>
* r600g: Use radeon pciid list for the family lookup tableBenjamin Franzke2011-06-072-481/+6
| | | | Reviewed-by: Alex Deucher <[email protected]>
* targets/egl: Support driver name lookup using pci listsBenjamin Franzke2011-06-073-71/+83
| | | | | | Make use of this in drm and wayland st/egl backends. Reviewed-by: Alex Deucher <[email protected]>
* tgsi: s/varient/variant/Brian Paul2011-06-071-2/+2
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* draw: rename draw_vs_varient.c to draw_vs_variant.cBrian Paul2011-06-073-2/+2
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* draw/llvm: whitespace, formatting fixesBrian Paul2011-06-071-38/+51
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* draw: s/1/TRUE/Brian Paul2011-06-071-2/+2
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* Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesaStéphane Marchesin2011-06-068-373/+430
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| * r600g: optimise the draw emission packets for r600/egDave Airlie2011-06-072-30/+37
| | | | | | | | | | | | This just reduces code size a bit for this chunk. Signed-off-by: Dave Airlie <[email protected]>
| * r600g: use an enabled list to track enabled blocks.Dave Airlie2011-06-074-35/+56
| | | | | | | | | | | | | | | | At the end of flushing we were scanning over 450 blocks with generally about 50 enabled. This reduces the scanning to just the list of enabled blocks. Signed-off-by: Dave Airlie <[email protected]>
| * r600g/winsys: overhaul resource range/blocks.Dave Airlie2011-06-074-65/+110
| | | | | | | | | | | | | | There isn't much point taking the overhead of range/block lookups on resources we aren't going to be getting resource registers at wierd offsets. Signed-off-by: Dave Airlie <[email protected]>
| * r600g: split out block initDave Airlie2011-06-071-46/+55
| | | | | | | | | | | | | | This just splits this function up as pre-cursor to reusing the internals of it. Signed-off-by: Dave Airlie <[email protected]>
| * r600g: move resource setting to its own structures.Dave Airlie2011-06-078-172/+140
| | | | | | | | | | | | | | | | | | resource setting could be a fair bit more lightweight, this patch just separates the resource structs from the standard reg tracking structs in the driver, later patches will improve the winsys. Signed-off-by: Dave Airlie <[email protected]>
| * r600g: only call bo loop if nbos is positive.Dave Airlie2011-06-071-17/+19
| | | | | | | | | | | | | | | | we don't need to loop over all the registers unless we have some bos in the block, also avoid setting the ctx flags, and move the optional stuff down below this chunk. Signed-off-by: Dave Airlie <[email protected]>
| * r600g: don't need to call the packet dirty function if not dirty.Dave Airlie2011-06-072-11/+16
| | | | | | | | | | | | also fix a unneeded dirty check and add a dirty check speedup. Signed-off-by: Dave Airlie <[email protected]>
* | i915g: Do generic remapping.Stéphane Marchesin2011-06-063-92/+119
|/ | | | | | With complex shaders there are often "holes" in the fs inputs, and we only have 8 tex coorsd to map those to. To fix this, we remap fs inputs to [0..8]. This lets us to run many more GLSL programs.
* i915g: implement more opcodes.Stéphane Marchesin2011-06-061-12/+82
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