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* gallium/radeon: Fix losing holes when allocating virtual address space.Michel Dänzer2012-08-161-1/+6
| | | | | | | | | If a hole exactly matches the allocated size plus alignment, we would fail to preserve the alignment as a hole. This would result in never being able to use the alignment area for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Merge holes when freeing virtual address space.Michel Dänzer2012-08-161-7/+38
| | | | | | | | | | Otherwise we'll likely end up with an ever increasing amount of ever smaller holes. Requires keeping the list ordered wrt offsets. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Make va_offset 64 bits wide.Michel Dänzer2012-08-161-1/+1
| | | | | | | | | | Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU virtual address space to 4GB anyway, but that will probably change sooner or later, and this would result in confusing error messages when running out of virtual address space even now. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* llvmpipe: Silence Coverity incorrect sizeof expression defect.Vinson Lee2012-08-151-1/+1
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* radeon/llvm: Enable if-cvtVincent Lejeune2012-08-151-0/+3
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Add callbacks needed by if-cvtVincent Lejeune2012-08-152-2/+151
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Lower branch/branch_cond into predicated jumpVincent Lejeune2012-08-157-145/+278
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Add a predicated JUMP instructionVincent Lejeune2012-08-151-0/+9
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-158-13/+125
| | | | | | | Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <[email protected]>
* r600g: Glue to handle predicate aware output from llvmVincent Lejeune2012-08-151-11/+22
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Fix instruction group merge when there are predicated insts.Vincent Lejeune2012-08-151-0/+18
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Do not use PV/PS if PRED_SEL does not matchVincent Lejeune2012-08-151-2/+4
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add support for predicatesVincent Lejeune2012-08-154-11/+18
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeonsi: move ps sampler state into PM4 streamChristian König2012-08-151-17/+7
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: move ps sampler views into PM4 streamChristian König2012-08-151-22/+7
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: move vertex state descriptors into PM4 streamChristian König2012-08-151-27/+9
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: add shader data infrastructureChristian König2012-08-153-2/+40
| | | | | | | | With this we can embed data for the shaders (like resource descriptors) into the PM4 stream. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: add support to fetch temps as vectorsChristian König2012-08-151-1/+11
| | | | | | | | Necessary for texture fetches with temp regs as source on SI. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Remove AMDGPUUtil.cppTom Stellard2012-08-158-81/+22
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* radeon/llvm: Cleanup AMDGPUUtil.cppApostolos Bartziokas2012-08-156-119/+95
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* radeon/llvm: Lower loads from USE_SGPR adddress space during DAG loweringTom Stellard2012-08-155-66/+50
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* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-159-66/+82
| | | | | | Psuedo instructions emulating live-in registers have been removed and their corresponding intrinsics are now being lowered during DAG lowering.
* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-153-22/+22
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* radeon/llvm: Force VTX_READ instructions to use same reg for src and dstTom Stellard2012-08-151-0/+14
| | | | | | I was seeing some GPU hangs that seemed to be cause by ALU instructions writing to the same register used as the source for VTX_READ. Adding this constraint to the VTX_READ instructions avoids this situation.
* radeonsi: fix build breakage after u_blitter changesMarek Olšák2012-08-151-3/+3
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* gallium/u_blitter: document custom meta helpersMarek Olšák2012-08-154-10/+19
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* r600g: disable handling of DISCARD_RANGEMarek Olšák2012-08-151-0/+2
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=53130
* r600g: implement timestamp query and get_timestamp hookMarek Olšák2012-08-154-2/+56
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable MSAA on evergreen by defaultMarek Olšák2012-08-151-3/+24
| | | | v2: add the DRM version check
* r600g: implement copying between MSAA texturesMarek Olšák2012-08-151-4/+10
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* r600g: implement MSAA color resolveMarek Olšák2012-08-156-3/+177
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* r600g: implement MSAA depth-stencil decompression and resolveMarek Olšák2012-08-156-35/+143
| | | | and integer textures, which are resolved the same as depth, I think.
* r600g: implement TXQ_LZ opcodeMarek Olšák2012-08-151-7/+15
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* r600g: implement MSAA rendering and texturing for evergreen and caymanMarek Olšák2012-08-154-26/+232
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* r600g: implement set_sample_maskMarek Olšák2012-08-156-17/+61
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* r600g: implement alpha-to-coverageMarek Olšák2012-08-156-6/+32
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* r600g: implement alpha-to-oneMarek Olšák2012-08-155-2/+20
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* r600g: remove support for 3-channel colorbuffersMarek Olšák2012-08-152-15/+0
| | | | We have no sampler support for them.
* configure.ac: bump libdrm_radeon requirement to 2.6.38Marek Olšák2012-08-151-1/+0
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* winsys/radeon: print error if CS is overflowedMarek Olšák2012-08-151-2/+6
| | | | and don't submit the CS to the kernel.
* gallium/u_blitter: implement X and Y texture flippingMarek Olšák2012-08-151-11/+26
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* gallium/u_blitter: implement blitting multisample resourcesMarek Olšák2012-08-159-105/+348
| | | | It can blit only one sample at a time (it should be called in a loop).
* gallium: add TGSI support for multisample texturesMarek Olšák2012-08-154-3/+11
| | | | | | | | | | The only allowed instructions are TXQ_LZ and TXF. TXQ_LZ is like TXQ, but without the LOD parameter (which is always zero with MSAA textures) The 3rd or the 4th texcoord component in TXF should contain the sample index for a 2D_MSAA or 2D_ARRAY_MSAA texture, respectively.
* gallium/tgsi: fix TGSI text parserMarek Olšák2012-08-151-77/+97
| | | | | | | | The problem was that the string matching succeeded e.g. for "2D" when there was actually "2D_MSAA" and then failed parsing "_MSAA". To prevent similar failures in the future, let's fix this kind of error everywhere.
* gallium/u_blit: set dst format from pipe_resource, not pipe_surfaceMarek Olšák2012-08-151-1/+1
| | | | | | We use it to decide whether we can use resource_copy_region. NOTE: This is a candidate for the 8.0 branch.
* gallium: make pipe_box signed in order to represent flipped blitsMarek Olšák2012-08-151-6/+6
| | | | This will be used by u_blitter.
* st/egl: Fix up for ClientVersion -> ClientMajorVersion rename.Michel Dänzer2012-08-151-3/+3
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53513 Signed-off-by: Michel Dänzer <[email protected]>
* mesa: Kill GL_ARB_shadow_ambient with fireIan Romanick2012-08-142-12/+2
| | | | | | | | | | No driver supports this extension, and it seems unlikely than any driver ever will. I think r300c may have supported it at one time, but that driver has already been removed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Inline immediate offset when lowering implicit parametersTom Stellard2012-08-141-4/+8
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* radeon/llvm: Use correct opcocde for BREAK_LOGICALNZ_i32Tom Stellard2012-08-142-12/+19
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