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* gallium: add user_ptr in pipe_resourceMarek Olšák2012-04-2410-0/+14
| | | | I need to access the pointer in st/mesa when I only have pipe_resource.
* u_vbuf: override draw_vboMarek Olšák2012-04-244-32/+33
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* u_vbuf: override create/bind/destroy_vertex_elements_stateMarek Olšák2012-04-248-82/+54
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* u_vbuf: override set_vertex_buffersMarek Olšák2012-04-2412-88/+86
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* u_vbuf: override set_index_bufferMarek Olšák2012-04-247-37/+61
| | | | This makes u_vbuf_mgr call the driver instead of the other way around.
* gallium/util: use cso_draw_arrays in util_draw_vertex_bufferMarek Olšák2012-04-241-5/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* cso: add set_index_buffer and draw_vbo passthrough functionsMarek Olšák2012-04-242-0/+48
| | | | | | v2: use util_draw_init_info Reviewed-by: Brian Paul <[email protected]>
* r300g/automake: add $ARCH_FLAGS and $OPT_FLAGSMarek Olšák2012-04-231-0/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g/automake: add $ARCH_FLAGS and $OPT_FLAGSMarek Olšák2012-04-231-0/+2
| | | | Reviewed-by: Tom Stellard <[email protected]>
* r600g: init vars to silence warningsBrian Paul2012-04-231-2/+2
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* radeon/llvm: Don't print an error message when there is no errorTom Stellard2012-04-231-2/+1
| | | | | A blank line with an empty error message was being printed even when the target lookup succeeded.
* radeon/llvm: Lower VCREATE_v4f32 for R600 and SITom Stellard2012-04-235-33/+22
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* r600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT}_SUBREGTom Stellard2012-04-236-88/+37
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* r600g/llvm: Only emit an instruction's explicit operandsTom Stellard2012-04-231-2/+2
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* r600g/llvm: Handle copies between vector registersTom Stellard2012-04-232-2/+21
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* r600g/llvm: Remove debugging hack from R600InstrInfo::copyPhysReg()Tom Stellard2012-04-231-4/+0
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* r600g/llvm: Tell the code emitter to ignore KILL and BUNDLETom Stellard2012-04-231-1/+3
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* r600/llvm: Add LOAD_VTX instructionTom Stellard2012-04-231-0/+13
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* r600g: Add hooks for the LLVM shader compilerTom Stellard2012-04-233-2/+304
| | | | | | | | | The LLVM backend can now be enabled for r600g by using the --enable-r600-llvm-compiler configure flag. If you configure with this flag, you can still use the default compiler by setting the envrionment variable R600_USE_LLVM=0 Reviewed-by: Alex Deucher <[email protected]>
* r600g: Add TGSI->LLVM implementation v2Tom Stellard2012-04-232-0/+330
| | | | | | v2: Add case for ARUBA in r600_llvm_gpu_string() Reviewed-by: Alex Deucher <[email protected]>
* radeon: Move radeon_llvm_emit.cpp declarations into their own headerTom Stellard2012-04-235-19/+58
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeon: Remove HAVE_LLVM ifdefsTom Stellard2012-04-231-10/+0
| | | | | | Only LLVM 3.1 is supported, so these are not necessary. Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix gpr number calculationVadim Girlin2012-04-231-0/+3
| | | | | Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tom Stellard <[email protected]>
* r600g: split add_reg into add_reg and add_reg_bo variantsDave Airlie2012-04-234-215/+193
| | | | | | | | | This shaves 2k off the final dri.so, and removes lots of pointless NULL, 0 passing. most like pointless - but it looked nicer to me. Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable GLSL130 on all cardsDave Airlie2012-04-221-3/+2
| | | | | | | | Alexandre Demers sent me some cayman results with no major problems. I'll rip out the env var in a week or so. Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable dual src blending on r600 cardsDave Airlie2012-04-211-1/+1
| | | | | | tested on my rv610 and it passes the tests with no hangs. Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable GLSL 1.30 for r600 classDave Airlie2012-04-211-1/+1
| | | | | | | | | Full piglit run on my rv610 with no regressions. This only leaves cayman, however my cayman is resisting my attempt to get through a full piglit run. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable glsl 1.30 on r700Dave Airlie2012-04-211-1/+1
| | | | | | | | I've done a piglit run on rv740 and confirmed no regressions. We don't get GL3 on r700 due to transform feedback being busted still. Signed-off-by: Dave Airlie <[email protected]>
* r600g: report INTEGERS cap if glsl130 is on.Dave Airlie2012-04-201-1/+2
| | | | | | | | | This cap is used by u_blitter to decide if it can use integers in vertex data. fixes some crashes with glsl130 in piglit Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable glsl 130 on evergreen.Dave Airlie2012-04-201-1/+3
| | | | | | | | | | | | I've done a piglit run on my SUMO machine and I see no regressions. Lots of things to fix (skip->fail), but hey maybe we can fix them if we can see them. I'll try and work my way across r600,700,cayman sometime if nobody else gets to them. Signed-off-by: Dave Airlie <[email protected]>
* r600g: disable I2F conversion for InstanceID if integers are supportedVadim Girlin2012-04-201-11/+16
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: store glsl_feature_level in the r600_screenVadim Girlin2012-04-202-1/+3
| | | | | | Signed-off-by: Vadim Girlin <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: Fix VGPR_BIT() definition.Michel Dänzer2012-04-191-1/+1
| | | | | | | | Fixes encoding of VOP3 shader instructions. The shift was wrong for source registers 2 and 3, and the resulting value was only 32 bits, so the shift in SICodeEmitter::VOPPostEncode() didn't work as intended.
* radeonsi: Replace magic numbers for vertex buffer resource.Michel Dänzer2012-04-191-4/+8
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* radeonsi: (User) SGPR related cleanups.Michel Dänzer2012-04-193-16/+33
| | | | | | Use the same user SGPRs for the same purpose in vertex and pixel shaders. Better calculation of the number of SGPRs to reserve.
* radeonsi: Fix sampler offsets for shader intrinsic.Michel Dänzer2012-04-191-2/+2
| | | | | The sampler number is in TGSI source register 1, and the S_LOAD_DWORD* instructions take offsets in DWORDs, not bytes.
* nv50,nvc0: prevent multiple flushes when user spins on get_query_resultChristoph Bumiller2012-04-192-19/+31
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* nv50/ir/opt: swap VP inputs to first source where possibleChristoph Bumiller2012-04-191-0/+17
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* radeonsi: MIMG shader instructions require waiting for the results.Michel Dänzer2012-04-191-0/+2
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* radeonsi: Replace more magic numbers for sampler state.Michel Dänzer2012-04-191-7/+7
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* radeonsi: Fix mip filter encoding in sampler state.Michel Dänzer2012-04-191-3/+3
| | | | Blits are starting to work.
* radeonsi: Set tiling mode index for depth/stencil buffers.Michel Dänzer2012-04-191-19/+37
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* svga: flush drawing before clearingBrian Paul2012-04-181-0/+3
| | | | | | | | | We don't normally clear immediately after drawing something. But as it was, the drawing would incorrectly appear after the clear. Fixes piglit clear-varray-2.0 failure. Reviewed-by: José Fonseca <[email protected]>
* pipebuffer: split up assertionBrian Paul2012-04-181-1/+2
| | | | | The problem with assert(a && b) is you don't know which term is zero when there's a failure.
* svga: return PIPE_OK instead of 0Brian Paul2012-04-181-1/+1
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* gallium/u_gen_mipmap: don't release vertex buffer at end of frame / in glFlushMarek Olšák2012-04-182-19/+4
| | | | | There's no reason to do that. The buffer being used for rendering is always mapped as unsynchronized.
* gallium/u_blit: don't release vertex buffer at end of frame / in glFlushMarek Olšák2012-04-182-18/+4
| | | | | There's no reason to do that. The buffer being used for rendering is always mapped as unsynchronized.
* gallium: remove PIPE_TRANSFER_NOOVERWRITE, use equivalent UNSYNCHRONIZEDMarek Olšák2012-04-183-3/+2
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* radeonsi: Improve calculation of number of pixel shader interpolants.Michel Dänzer2012-04-181-23/+7
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* radeonsi: Fix calculation of pitch value in sampler view state.Michel Dänzer2012-04-181-4/+2
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