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* ac: select the GFX ring when halting waves with UMR on GFX10Samuel Pitoiset2019-07-081-1/+1
| | | | | | | | GFX10 has two rings, so UMR want to know which one to halt. Select the first one by default. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* llvmpipe: enable ARB_shader_storage_buffer_objectDave Airlie2019-07-072-4/+5
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: add support for shader buffer binding.Dave Airlie2019-07-078-2/+100
| | | | | | | This add support for setting shader buffers and passing them to draw or binding them to the fragment shader jit. Reviewed-by: Roland Scheidegger <[email protected]>
* draw: add shader buffer interfaces.Dave Airlie2019-07-074-1/+57
| | | | | | | This adds the interface to add mapped shader buffers, and sets up the jit linkage for them. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: add buffer operations to the tgsi->llvm conversion.Dave Airlie2019-07-073-4/+315
| | | | | | | | | | | | This adds load, store and atomic operations. These operations have to respect the exec_mask, and can't operate in lanes where the execute is off. This is needed to avoid side effects seen outside the shaders. There is also bounds checking on the ssbo accesses vs the size ptr. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: move mask_vec function up higher so it can be reused.Dave Airlie2019-07-071-14/+15
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* tgsi: denote which load/store/atomic channels are unsignedDave Airlie2019-07-071-0/+12
| | | | | | llvmpipe will need this info. Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: add support for ssbo to the fragment shader jit.Dave Airlie2019-07-073-2/+25
| | | | | | This just adds the ssbo ptrs to the jit fragment shader api. Reviewed-by: Roland Scheidegger <[email protected]>
* draw: add support for ssbo ptrs to jit tables.Dave Airlie2019-07-072-3/+49
| | | | | | This adds ssbo/num_ssbo ptrs to the vs/gs jit tables. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: add some basic SSBO limits. (v2)Dave Airlie2019-07-071-0/+4
| | | | | | v2: update ssbo size Reviewed-by: Roland Scheidegger <[email protected]>
* util: add util_copy_shader_buffer.Dave Airlie2019-07-071-0/+16
| | | | | | This just adds an inline to copy a pipe_shader_buffer. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: add ssbo pointers to the soa build api.Dave Airlie2019-07-075-8/+20
| | | | | | Need to pass ssbo + ssbo size pointers just like constants. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: add compare exchange wrapperDave Airlie2019-07-073-1/+39
| | | | | | This just pulls the wrapper from LLVM for older versions Reviewed-by: Roland Scheidegger <[email protected]>
* vertex shader: add exec masking (v2)Dave Airlie2019-07-071-3/+10
| | | | | | | | | | As suggested by Roland this is just a compare of fetch_max vs the counter, much simpler than my original spaghetti code. We require the vertex shader to have an exec mask to get proper ssbo/image load/atore/atomics semantics Reviewed-by: Roland Scheidegger <[email protected]>
* virgl: Hide internal virgl_resource functionsAlexandros Frantzis2019-07-062-166/+157
| | | | | | | | | | | | Since the transition to virgl_resource_transfer_map(), several previously public virgl_resource functions are not required to be public anymore. We also move the functions earlier in the file so they can be used without functions declarations. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Use virgl_resource_transfer_map for texturesAlexandros Frantzis2019-07-062-60/+4
| | | | | | | | Replace custom texture map code (for maps which don't require resolve) with virgl_resource_transfer_map. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Use virgl_resource_transfer_map for buffersAlexandros Frantzis2019-07-061-79/+1
| | | | | | | Replace custom buffer map code with virgl_resource_transfer_map. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* virgl: Introduce virgl_resource_transfer_mapAlexandros Frantzis2019-07-062-0/+92
| | | | | | | | | Normal mapping of buffers and textures uses almost identical logic. This commit extracts the this logic in the form of the virgl_resource_transfer_map() helper function. Signed-off-by: Alexandros Frantzis <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* iris: Use a uint16_t for key sizesJason Ekstrand2019-07-041-1/+1
| | | | | | | sizeof(struct brw_vs_prog_key) == 324. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* ac: destroy passes in ac_destroy_llvm_compilerMarek Olšák2019-07-041-2/+0
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: only set ac_dlc in ac_llvm_build.cMarek Olšák2019-07-041-6/+4
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: replace glc,slc with cache_policy for loadsMarek Olšák2019-07-043-18/+15
| | | | | | cosmetic change Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: replace glc,slc with cache_policy for storesMarek Olšák2019-07-043-21/+18
| | | | | | cosmetic change Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* etnaviv: implement buffer compressionJonathan Marek2019-07-048-49/+65
| | | | | | | | | | | | | | | Vivante GPUs have lossless buffer compression using the tile-status bits, which can reduce memory access and thus improve performance. This patch only enables compression for "V4" compression GPUs, but the implementation is tested on GC2000(V1) and GC3000(V2). V1/V2 compresssion looks absolutely useless, so it is not enabled. I couldn't test if this patch breaks MSAA, because it looks like MSAA is already broken. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: detect v4 compressionJonathan Marek2019-07-043-0/+11
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: rs: don't use etna_compatible_rs_format when possibleJonathan Marek2019-07-041-2/+9
| | | | | | | This mirrors the change in blt. RS cares about this for msaa/compression. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: combine translate_ts_sampler_format/translate_msaa_formatJonathan Marek2019-07-046-95/+92
| | | | | | | Both translate the same thing, so just add the missing cases into one. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix compression format not set correctly in TS_MEM_CONFIGJonathan Marek2019-07-042-3/+6
| | | | | | | VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT() needs to be used. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: set correct ts_clear_value for BLT engineJonathan Marek2019-07-041-2/+4
| | | | | | | | BLT engine uses all ones to clear TS, set ts_clear_value to match that. Note: ts_clear_value is never used with BLT engine. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: remove initial CPU ts clearJonathan Marek2019-07-041-7/+0
| | | | | | | | Since we have "ts_valid" to avoid using uncleared ts, this memset serves no purpose. Also it is broken because it doesn't use cpu_prep/cpu_fini. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: implement TS_MODE for GC7000LJonathan Marek2019-07-0410-12/+35
| | | | | | | GC7000L has a TS mode with larger tiles, which improves performance. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix ts size calculationJonathan Marek2019-07-041-4/+3
| | | | | | | | | | | The size of the TS is screen->specs.bits_per_tile bits per tile, with each tile being 64 bytes of the resource. This gives the same result for 32bpp formats, but reduces the size of TS for 16bpp formats by 2. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: update headers from rnndbJonathan Marek2019-07-049-99/+96
| | | | | | | Update to etna_viv commit 8a8b13a and use new names in the code. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radeonsi: Fix some warnings.Bas Nieuwenhuizen2019-07-042-2/+2
| | | | | | | | | | | | | | ../mesa/src/gallium/drivers/radeonsi/si_compute_blit.c: In function ‘si_clear_buffer’: ../mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:195:11: warning: unused variable ‘clear_alignment’ [-Wunused-variable] unsigned clear_alignment = MIN2(clear_value_size, 4); ^~~~~~~~~~~~~~~ [23/60] Compiling C object 'src/gallium/drivers/radeonsi/3cdc30e@@radeonsi@sta/si_compute_prim_discard.c.o'. ../mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c: In function ‘si_prepare_prim_discard_or_split_draw’: ../mesa/src/gallium/drivers/radeonsi/si_compute_prim_discard.c:1106:7: warning: unused variable ‘compute_has_space’ [-Wunused-variable] bool compute_has_space = sctx->ws->cs_check_space(cs, need_compute_dw, false); Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* amd/common: move ac_shader_{binary,reloc} into r600 and renameNicolai Hähnle2019-07-044-36/+65
| | | | | | | | They are no longer used by radeonsi or radv. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* panfrost: Take into account off-screen FBOsTomeu Vizoso2019-07-041-4/+6
| | | | | | | | In that case, ctx->pipe_framebuffer.cbufs[0] can be NULL. Signed-off-by: Tomeu Vizoso <[email protected]> Cc: Boris Brezillon <[email protected]> Fixes: 5375d009be18 ("panfrost: Pass referenced BOs to the SUBMIT ioctls")
* iris: Fix MOCS for grid surfaceKenneth Graunke2019-07-031-3/+4
| | | | Hardcoding 4 is bad; we have a function for this now.
* iris: Minor tidyingKenneth Graunke2019-07-038-62/+5
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* gallium/u_blitter: add return to fix the buildMarek Olšák2019-07-031-0/+1
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* radeonsi/gfx10: fix legacy GSMarek Olšák2019-07-031-1/+4
| | | | | | | | LLVM doesn't insert s_waitcnt_vscnt before GS_DONE. There was also the crash in legacy GS copy shader. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: disable clear stateNicolai Hähnle2019-07-032-8/+5
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: disable DPBBNicolai Hähnle2019-07-031-0/+5
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: disable SDMANicolai Hähnle2019-07-031-0/+2
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: determine the rasterization primitive type accurately (v2)Marek Olšák2019-07-034-8/+38
| | | | | | v2: reworked version to fix bugs and make it more efficient Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: consolidate & improve input_prim determination for NGGMarek Olšák2019-07-033-8/+21
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac: rework ac_build_waitcnt for gfx10Marek Olšák2019-07-032-9/+8
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: implement si_shader_vsMarek Olšák2019-07-033-20/+30
| | | | | | Only used with tessellation + GS instancing. Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: unpack GS invocation IDMarek Olšák2019-07-031-4/+11
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: jump over the shader query atomic if the queries are disabledMarek Olšák2019-07-033-0/+12
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi/gfx10: cosmetic changesMarek Olšák2019-07-035-24/+26
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
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