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* svga: avoid freeing non-malloced memoryBrian Paul2016-03-291-10/+2
| | | | | | | | | | | svga_shader_expand() will fall back to using non-malloced memory for emit.buf if malloc fails. We should check if the memory is malloced before freeing it in the error path of svga_tgsi_vgpu9_translate. Original patch by Thomas Hindoe Paaboel Andersen <[email protected]>. Remove trivial svga_destroy_shader_emitter() function, by BrianP. Signed-off-by: Brian Paul <[email protected]>
* nvc0/ir: move load/store lowering pass to handleLDST()Samuel Pitoiset2016-03-292-54/+61
| | | | | | | Having all this code in a big switch is not really a good pratice. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/vdpau: implement the new DMA-buf based interop v2Christian König2016-03-294-3/+116
| | | | | | | | | That should allow us to get away from passing internal structures around. v2: rebased Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/vdpau: move FormatRGBAToPipe into the interopChristian König2016-03-295-28/+73
| | | | | | | We are going to need that in the Mesa state tracker as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/vdpau: add new interop interfaceChristian König2016-03-292-1/+100
| | | | | | | | Use DMA-buf for the VDPAU interop interface instead of using internal structures. Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/vdpau: use linear layout for output surfacesChristian König2016-03-291-1/+2
| | | | | | | | Works around a bug in radeonsi and tiling is actually not very beneficial in this use case. Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeonsi: ignore PIPE_BIND_LINEAR in si_is_format_supported v2Christian König2016-03-291-0/+5
| | | | | | | | | Linear layout should work for all not compressed or depth/stencil formats. v2: restrict it a bit more Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: use a different offset for buffers and surfacesSamuel Pitoiset2016-03-294-28/+74
| | | | | | | | | | To not overwrite buffers and surfaces information, we need to use a different offset in the driver constant buffer. Currently, OP_SUQ is only supported for buffers but this will be slightly updated for images support. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* vc4: Remove unused include from vc4_nir_lower_txf_ms.cRhys Kidd2016-03-281-1/+0
| | | | | | | | Found with grep and inspection. Test compiled on RPi hw. Assists any future effort to remove TGSI as an intermediate stage. Signed-off-by: Rhys Kidd <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* freedreno/ir3: fix for load_front_face intrinsicRob Clark2016-03-281-1/+8
| | | | | | | Seems like trying to widen in the same instruction as the add.s does a non-sign-extending widen. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix compiler warnRob Clark2016-03-281-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* nvc0: make sure to disable fetches from previously-set VBOs when blittingIlia Mirkin2016-03-281-0/+2
| | | | | | | We disable the vertex attributes, but also disable the VBO fetch details as well, just in case. Not known to fix anything. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: disable primitive restart and index bias during blitsIlia Mirkin2016-03-281-0/+11
| | | | | | | | | | | | | | | | Back in the dawn of time, we used to do immediate uploads for the vertex data, and all was well. However Maxwell dropped support for immediate vertex data, so we started feeding in a VBO (in all cases). But we forgot to disable some things that apply in such cases, specifically primitive restart and index bias. The latter was causing WoW and other Blizzard games trouble as they use a pattern where they draw with a base vertex (aka index bias), followed by texture uploads (aka blits, internally). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526 Cc: "11.1 11.2" <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Karol Herbst <[email protected]>
* nvc0/ir: fix picking of coordinates from tex instruction for textureGradIlia Mirkin2016-03-281-1/+11
| | | | | | | | | | | On Fermi, there's an argument in front of the coords that combines array and indirect handle, while on Kepler the array and the indirect handle are separate (and in front of the coords). We were previously only accounting for the array bit of it, if there were an indirect access it wouldn't be counted in the formula. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.1 11.2" <[email protected]>
* nv50/ir: saturate depth writesIlia Mirkin2016-03-281-1/+4
| | | | | | | | | | | Apparently there's no post-FS clamping logic, so we have to do this by hand. The depth will never be outside of the 0..1 range, even on floating point zeta buffers, so this should be safe. Fixes dEQP-GLES3.functional.fbo.depth.*clamp.* which tests writing invalid values on various zeta buffer formats. Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/util: fix up inaccurate behavior of util_framebuffer_state_equal (v2)Marek Olšák2016-03-281-5/+5
| | | | | | v2: move the nr_cbufs check above the loop Reviewed-by: Ilia Mirkin <[email protected]> (v1)
* gallium/p_context.h: Make comment more readableEdward O'Callaghan2016-03-271-1/+1
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeon/r600: Fix return type in failure branchEdward O'Callaghan2016-03-271-1/+1
| | | | | | | | Commit `d4e847ea` introduced a warning about making an integer from a pointer without a cast, fix it here. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeon/r600_query.c: Minor style fixEdward O'Callaghan2016-03-271-1/+1
| | | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* virgl: drop next shader property for now.Dave Airlie2016-03-261-0/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* st/xa: emit sampler view declarations in shadersBrian Paul2016-03-251-0/+19
| | | | | | | Fixes recent regressions with the VMware gallium driver. Reviewed-by: Charmaine Lee <[email protected]> Tested-by: Charmaine Lee <[email protected]>
* swr: [rasterizer jitter] Fix MASKLOADD AVX prototype (float -> i32)Tim Rowley2016-03-251-1/+1
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* swr: [rasterizer core] NUMA optimizations...Tim Rowley2016-03-255-65/+105
| | | | | - Affinitize hot-tile memory to specific NUMA nodes. - Only do BE work for macrotiles assoicated with the numa node
* swr: [rasterizer jitter] Fix logic bug for alpha-to-coverage.Tim Rowley2016-03-251-2/+11
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* swr: [rasterizer core] Fix Compute workitem retirementTim Rowley2016-03-254-31/+22
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* swr: [rasterizer core] Cleanup state ring arena after last draw that ↵Tim Rowley2016-03-253-2/+14
| | | | | | references it completes Rather than waiting for the API thread to re-use it.
* swr: [rasterizer jitter] add missing include for llvm jiteventsTim Rowley2016-03-251-0/+4
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* swr: [rasterizer core] Reduce Arena blocksize to 128KB (from 1MB).Tim Rowley2016-03-251-3/+7
| | | | | With global allocator this doesn't seem to affect performance at all. Overall memory consumption drops by up to 85%.
* swr: [rasterizer core] One last pass at Arena optimizationsTim Rowley2016-03-251-15/+15
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* swr: [rasterizer core] CachedArena optimizationsTim Rowley2016-03-253-210/+161
| | | | | | Reduce list traversal during Alloc and Free. Add ability to have multiple lists based on alloc size (not used for now)
* swr: [rasterizer jitter] support llvm-svnTim Rowley2016-03-256-12/+37
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* swr: [rasterizer core] Globally cache allocated arena blocks for fast ↵Tim Rowley2016-03-258-46/+168
| | | | re-allocation.
* swr: [rasterizer] more arena workTim Rowley2016-03-255-10/+110
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* swr: [rasterizer core] Add clipping against user clip distances in the ↵Tim Rowley2016-03-251-2/+12
| | | | NullPS backend.
* swr: [rasterizer core] Arena optimizations - preparing for global allocator.Tim Rowley2016-03-255-187/+131
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* swr: [rasterizer core] Reset DrawContext arena at end of draw rather than ↵Tim Rowley2016-03-252-21/+4
| | | | | | | upon reclaim of DC Keeps overall memory consumption lower. Also, remove unused knobs.
* swr: [rasterizer core] Add clipping of user clip planes in clipper.Tim Rowley2016-03-251-0/+86
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* swr: [rasterizer] Reduce max in-flight draws to 96 (by default)Tim Rowley2016-03-251-1/+1
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* swr: [rasterizer] Fix run-time check assertsTim Rowley2016-03-252-8/+7
| | | | | One innocuous (uninitialized variable), and one not so innocuous (stack corruption).
* swr: [rasterizer jitter] signed immediate builderTim Rowley2016-03-252-0/+8
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* swr: [rasterizer common] changes for cygwinTim Rowley2016-03-251-1/+4
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* swr: [rasterizer] code styling and update copyrightsTim Rowley2016-03-2510-328/+328
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* swr: [rasterizer core] Guard against enquing work to invalid hot tilesTim Rowley2016-03-251-0/+5
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* swr: [rasterizer] Stop setting viewport size to larger than hottile arrayTim Rowley2016-03-251-0/+6
| | | | Guard against enquing work to invalid tiles
* swr: [rasterizer] Discard work + misc fixesTim Rowley2016-03-259-28/+119
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* swr: [rasterizer] remove use of BYTE typeTim Rowley2016-03-2515-74/+65
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* swr: [rasterizer core] Fix crash that can occur when switching contextsTim Rowley2016-03-253-1/+22
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* swr: [rasterizer] remove unused knobTim Rowley2016-03-251-8/+0
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* swr: [rasterizer core] subcontext reworkTim Rowley2016-03-257-52/+61
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* swr: [rasterizer common] add _simd_s[rl]lv_epi32Tim Rowley2016-03-251-0/+115
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