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* svga: fix test for unfilled triangles fallbackBrian Paul2016-05-263-6/+43
| | | | | | | VGPU10 actually supports line-mode triangles. We failed to make use of that before. Reviewed-by: Charmaine Lee <[email protected]>
* svga: clean up and improve comments in svga_draw_private.hBrian Paul2016-05-261-4/+8
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* util/indices: implement unfilled (tri->line) conversion for adjacency primsBrian Paul2016-05-262-2/+38
| | | | | | | | Tested with new piglit gl-3.2-adj-prims test. v2: re-order trisadj and tristripadj code, per Roland. Reviewed-by: Roland Scheidegger <[email protected]>
* util/indices: implement provoking vertex conversion for adjacency primitivesBrian Paul2016-05-263-3/+134
| | | | | | Tested with new piglit gl-3.2-adj-prims test. Reviewed-by: Roland Scheidegger <[email protected]>
* util/indices: assert that the incoming primitive is a triangle typeBrian Paul2016-05-261-0/+5
| | | | | | | The unfilled index translator/generator functions should only be called when the primitive mode is one of the triangle types. Reviewed-by: Roland Scheidegger <[email protected]>
* util/indices: formatting, whitespace fixes in u_unfilled_indices.cBrian Paul2016-05-261-12/+7
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* util/indices: improve comments in u_indices.hBrian Paul2016-05-261-3/+29
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* svga: fix primitive mode (point/line/tri) test for unfilled primitivesBrian Paul2016-05-262-2/+2
| | | | | | | | | The original mode test was valid before we had GS support. Regression tested with full piglit run. Though, I don't think we have any piglit tests that exercise drawing unfilled adjacency primitives. Reviewed-by: Charmaine Lee <[email protected]>
* nvc0: invalidate textures/samplers between 3D and CP on FermiSamuel Pitoiset2016-05-262-0/+27
| | | | | | | | | | | Like constant buffers, samplers and textures are aliased on Fermi and we need to invalidate the state when switching from 3D to CP and vice versa. This fixes rendering issues in the UE4 demos. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* compiler: Move glsl_to_nir to libglsl.laJason Ekstrand2016-05-261-1/+1
| | | | | | | | Right now libglsl.la depends on libnir.la so putting it in libnir.la adds a dependency on libglsl.la that goes the wrong direction. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* radeonsi: Allow TES distribution between shader engines.Bas Nieuwenhuizen2016-05-264-15/+40
| | | | | | | | | | | | | The R_028B50_VGT_TESS_DISTRIBUTION value is copied from amdgpu-pro. Smaller values in the ACCUM fields seem to decrease the performance advantage from this patch, higher values don't seem to matter. v2: Add distribution mode field enums. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Process multiple patches per threadgroup.Bas Nieuwenhuizen2016-05-261-15/+35
| | | | | | | | | | | | | | | | | | | | | | | Using more than 1 wave per threadgroup does increase performance generally. Not using too many patches per threadgroup also increases performance. Both catalyst and amdgpu-pro seem to use 40 patches as their maximum, but I haven't really seen any performance increase from limiting the number of patches to 40 instead of 64. Note that the trick where we overlap the input and output LDS does not work anymore as the insertion of the tess factors changes the patch stride. v2: - Add comment about LDS assumptions. - Add constant for buffer size. - Fix code style. v3: - Correct limits for not splitting patches between waves. - Set max num_patches to 40 as in the proprietary driver. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add barrier before writing the tess factors.Bas Nieuwenhuizen2016-05-261-0/+6
| | | | | | | | The factors may be stored to LDs by another invocation than the invocation for vertex 0. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Enable dynamic HS.Bas Nieuwenhuizen2016-05-262-5/+16
| | | | | | | | | | This allows running the TES on different CU's than the TCS which results in performance improvements. v2: Only write the control word from one invocation. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Remove LDS layout user SGPR's from TES.Bas Nieuwenhuizen2016-05-263-13/+10
| | | | | | | | They are unused. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Use buffer loads and stores for passing data from TCS to TES.Bas Nieuwenhuizen2016-05-261-16/+50
| | | | | | | | | | | | | | | | We always try to use 4-component loads, as LLVM does not combine loads and they bypass the L1 cache. We can't use a similar strategy for stores and this is especially notable with the tess factors, as they are often set with separate MOV's per component in the TGSI. We keep storing to LDS and the LDS space, so we can load the outputs later, either due to the shader, of for wrting the tess factors. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Store inputs to memory when not using a TCS.Bas Nieuwenhuizen2016-05-263-0/+49
| | | | | | | | | | | | | | | | | We need to copy the VS outputs to memory. I decided to do this using a shader key, as the value depends on other shaders. I also switch the fixed function TCS over to monolithic, as otherwisze many of the user SGPR's need to be passed to the epilog, which increases register pressure, or complexity to avoid that. The main body of the fixed function TCS is not that interesting to precompile anyway, since we do it on demand and it is very small. v2: Use u_bit_scan64. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add offchip buffer address calculation.Bas Nieuwenhuizen2016-05-261-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of creating a memory area per patch and per vertex, we put the same attribute of every vertex & patch together. Most loads and stores access the same attribute across all lanes, only for different patches and vertices. For the TCS this results in tightly packed data for 4-component stores. For the TES this is not the case as within a patch the loads often also access the same vertex. However if there are < 4 vertices/patch, this still results in a reduction of the number of cache lines. In the LDS situation we only do better than worst case if the data per patch < 64 bytes, which due to the tessellation factors is pretty much never. We do not use hardware swizzling for this. It would slightly reduce the number of executed VALU instructions, but I had issues with increased wait times that I haven't been able to solve yet. Furthermore, the tbuffer_store intrinsic does not support both VGPR offset and an index, so we have a problem storing indirectly indexed outputs. This can be solved by temporarily storing arrays in LDS and then copying them, but I don't think that is worth the effort. The difference in VALU cycles hardware swizzling gives is about 0.2% of total busy cycles. That is without handling the array case. I chose for attributes instead of components as they are often accessed together, and the software swizzling takes VALU cycles for calculating offsets. v2: - Rename functions to get_tcs_tes_buffer_address. - multiply by 16 as late as possible. - Use tgsi_full_src_register_from_dst. - Remove some bad comments. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add user SGPR for the layout of the offchip buffer.Bas Nieuwenhuizen2016-05-263-4/+20
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Use correct parameter index for LS_OUT_LAYOUT.Bas Nieuwenhuizen2016-05-261-3/+4
| | | | | | | | | This happens to be in the right position, but that changes when TCS/TES get new parameters. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add buffer load functions.Bas Nieuwenhuizen2016-05-261-0/+114
| | | | | | | | | | v2: - Use llvm.admgcn.buffer.load instrinsics for new LLVM. - Code style fixes. v3: - Code style fix. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Define build_tbuffer_store_dwords earlier to support new users.Bas Nieuwenhuizen2016-05-261-69/+69
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add offchip tessellation parameters.Bas Nieuwenhuizen2016-05-263-6/+34
| | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Add buffer for offchip storage between TCS and TES.Bas Nieuwenhuizen2016-05-264-0/+23
| | | | | | | | | | | The buffer is quite large, but should only be allocated if the application uses tessellation. Most non-games don't. v2: - Use the correct register for SI. - Add define for block size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: fix coverity out-of-bounds warningRob Clark2016-05-261-0/+3
| | | | | | | | | CID 1271532 (#1 of 1): Out-of-bounds read (OVERRUN)34. overrun-local: Overrunning array of 2 16-byte elements at element index 2 (byte offset 32) by dereferencing pointer &inst.Dst[i]. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* tgsi: fix out of bounds accessRob Clark2016-05-261-1/+1
| | | | | | | | | | | | Not sure why coverity calls this an out-of-bounds read vs out-of-bounds write. CID 1358920 (#1 of 1): Out-of-bounds read (OVERRUN)9. overrun-local: Overrunning array r of 3 16-byte elements at element index 3 (byte offset 48) using index chan (which evaluates to 3). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: allow to monitor MP perf counters with compute shadersSamuel Pitoiset2016-05-262-19/+55
| | | | | | | | | | | | | | | | | | To read out MP perf counters we use a compute shader and need to upload input data like a 64-bits addr used to store the values and a sequence ID for synchronization. Currently, this input data is uploaded as user uniforms which means that it's sticked to c0[], but if a compute shader from a real application is used, monitoring those performance counters will just overwrite some data and miserably crash. Instead, sticking the 64-bits addr and the sequence into the driver constant buffer seems like much better and will allow to monitor counters with GL 4.3 apps. Tested on GF119 and GK110, but should not hurt anything on GK104. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: add the kernel version into the renderer stringMarek Olšák2016-05-261-3/+9
| | | | | | | | | | | Example: Gallium 0.4 on AMD TONGA (DRM 3.2.0 / 4.5.0, LLVM 3.9.0) My kernel version is pretty long already (4.5.0-amd-01025-g32791c1) and adding "kernel" into the string would make too it long for glxinfo to display. Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: add back multithreaded command submissionMarek Olšák2016-05-266-131/+341
| | | | | | | | | | | | | | | Ported from the initial amdgpu winsys from the private AMD branch. The thread creates the buffer list, submits IBs, and cleans up the submission context, which can also destroy buffers. 3-5% reduction in CPU overhead is expected for apps submitting a lot of IBs per frame. This is most visible with DMA IBs. v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs add another amdgpu_cs_sync_flush call into amdgpu_bo_map Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/tgsi: use _mesa_roundevenf in micro_rndLars Hamre2016-05-261-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Fixes the following piglit tests (for softpipe): /spec/glsl-1.30/execution/built-in-functions/... fs-roundeven-float fs-roundeven-vec2 fs-roundeven-vec3 fs-roundeven-vec4 vs-roundeven-float vs-roundeven-vec2 vs-roundeven-vec3 vs-roundeven-vec4 /spec/glsl-1.50/execution/built-in-functions/... gs-roundeven-float gs-roundeven-vec2 gs-roundeven-vec3 gs-roundeven-vec4 Signed-off-by: Lars Hamre <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: add note about where the viewport mask would goIlia Mirkin2016-05-261-0/+1
| | | | | | | Not piping this all the way through yet, but no better place to note this down. This will can be used with NV_viewport_array2. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable 32 textures on kepler+Ilia Mirkin2016-05-262-3/+3
| | | | | | | | | For fermi, this likely will require use of linked tsc mode. However on bindless architectures, we can have as many as we want. As it stands, the AUX_TEX_INFO has 32 teture handles reserved. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* swr: [rasterizer] Correctly select optimized primitive assembly.Bruce Cherniak2016-05-257-9/+17
| | | | | | | | Indexed primitives were always using cut-aware primitive assembly, whether primitive_restart was enabled or not. Correctly pass down primitive_restart and select optimized PA when possible. Reviewed-by: Tim Rowley <[email protected]>
* freedreno/ir3: cmdline compiler for glslRob Clark2016-05-252-14/+77
| | | | | | | | Use glsl/libstandalone.la to add support for taking glsl src files (in addition to .tgsi) as input. Then glsl->nir and feed the result into the ir3 backend as normal. Signed-off-by: Rob Clark <[email protected]>
* nvc0: add descriptions for hardware perf counters/metricsSamuel Pitoiset2016-05-252-70/+353
| | | | | | | | | The GALLIUM_HUD does not yet expose a description for each events, but this might be useful for developers who want to have a long description of hw perf counters directly in the source code. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* scons: whitespace cleanupGiuseppe Bilotta2016-05-256-10/+10
| | | | | | | | | | This text transformation was done automatically via the following shell command: $ find -name SCons\* -exec sed -i s/\\s\\+$// '{}' \; Signed-off-by: Giuseppe Bilotta <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* tgsi: print TGSI_PROPERTY_NEXT_SHADER value as string, not an integerBrian Paul2016-05-252-0/+25
| | | | | | | | | Print "GEOM" instead of "2", for example. v2: also update the text parsing code, per Ilia. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: s/6/PIPE_SHADER_TYPES/ for tgsi_processor_type_names array sizeBrian Paul2016-05-251-1/+1
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa_glinterop: make GL interop version field bidirectionalEmil Velikov2016-05-241-1/+8
| | | | | | | | | | | | | | This allows clear and easy communication between the two. Caller: Requesting information (struct vN) Callee: I know how to deal with older version (vN-1) only. Here is your data and the version I support. Caller: Older version ? Sure I'll cap all access to the fields provided by the older version (vN-1) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* mesa_glinterop: drop mesa_glinterop_device_info::interop_versionEmil Velikov2016-05-241-2/+0
| | | | | | | | | | | | One cannot use a single version to control both export_in and export_out versions. Using this forces us to always extend/bump both structs at the same time. An alternative scheme is coming with next patch. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* st/dri: add note about GL interop version checksEmil Velikov2016-05-241-2/+4
| | | | | | | | ... and make them more explicit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* mesa_glinterop: rename MESA_GLINTEROP_INVALID_{VALUE,VERSION}Emil Velikov2016-05-241-2/+2
| | | | | | | | Be more explicit what it actually does. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* mesa_glinterop: s/struct_version/version/Emil Velikov2016-05-241-2/+2
| | | | | | | | OCD polish for consistency with other mesa interfaces. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* mesa_glinterop: use consistent naming scheme for GL interopEmil Velikov2016-05-241-3/+3
| | | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Tom Stellard <[email protected]>
* swr: [rasterizer] remove containers.hppTim Rowley2016-05-246-215/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] remove utility dead codeTim Rowley2016-05-243-257/+0
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] buckets fixesTim Rowley2016-05-245-25/+49
| | | | | | | | | | | | | | | 1. Don't clear bucket descriptions to fix issues with sim level buckets getting out of sync. 2. Close out threadviz file descriptors in ClearThreads(). 3. Skip buckets for jitter based buckets when multithreaded. We need thread local storage through llvm jit functions to be fixed before we can enable this. 4. Fix buckets StopCapture to correctly detect capture complete. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] move centroid setup out of CalcCentroidBarycentricsTim Rowley2016-05-242-15/+20
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] implement InstanceID/VertexID in fetch jitTim Rowley2016-05-242-173/+336
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* nvc0: expose robust buffer accessIlia Mirkin2016-05-231-1/+1
| | | | | | | We apparently pass all the relevant CTS tests. There are probably some shortcomings, but they can be addressed down the line. Signed-off-by: Ilia Mirkin <[email protected]>
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