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* radeonsi: remove si_vid_join_surfaces and use combined planar allocationsMarek Olšák2019-10-096-157/+50
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: allocate planar multimedia formats in 1 bufferMarek Olšák2019-10-093-34/+124
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vl: use u_format in vl_video_buffer_formatsMarek Olšák2019-10-096-112/+31
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/u_tests: test NV12 allocation and exportMarek Olšák2019-10-091-0/+159
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: add planar format layouts and helpersMarek Olšák2019-10-094-7/+108
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: remove enum numbering from util_format_layoutMarek Olšák2019-10-091-9/+9
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Disable fast clears when running with INTEL_DEBUG=nofcCaio Marcelo de Oliveira Filho2019-10-091-0/+6
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* llvmpipe: avoid left-shifting a negative number.Maya Rashish2019-10-093-6/+6
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Maya Rashish <[email protected]>
* lima/ppir: don't clone texture loadsVasily Khoruzhick2019-10-092-73/+0
| | | | | | | | | Cloning texture loads isn't a good idea since we may move it into a block that is not shared between all the invocations of the shader. We'd like to avoid that since it may result in undefined behavior. Reviewed-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Implement the Broadwell NP Z PMA Stall FixKenneth Graunke2019-10-085-2/+209
| | | | | | | | | This should help avoid stalls in the pixel mask array in certain non-promoted depth cases. It especially helps for Z16, as each bit in the PMA corresponds to two pixels when using Z16, as opposed to the usual one pixel. Improves performance in GFXBench5 TRex by 22% (n=1).
* iris: Properly unreference extra VBOs for draw parametersKenneth Graunke2019-10-081-3/+3
| | | | | | | | | bound_vertex_buffers doesn't include extra draw parameters buffers. Tracking this correctly is kind of complicated, and iris_destroy_state isn't exactly in a hot path, so just loop over all VBO bindings. Fixes: 4122665dd90 (iris: Enable ARB_shader_draw_parameters support) Reported-by: Sergii Romantsov <[email protected]>
* panfrost: Draw the wallpaper when only depth/stencil bufs are clearedBoris Brezillon2019-10-082-3/+15
| | | | | | | | | When only the depth/stencil bufs are cleared, we should make sure the color content is reloaded into the tile buffers if we want to preserve their content. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Make sure a clear does not re-use a pre-existing batchBoris Brezillon2019-10-083-1/+32
| | | | | | | | | | | | | | glClear()s are expected to be the first thing GL apps do before drawing new things. If there's already an existing batch targetting the same FBO that has draws attached to it, we should make sure the new clear gets a new batch assigned to guaranteed that the FB content is actually cleared with the requested color/depth/stencil values. We create a panfrost_get_fresh_batch_for_fbo() helper for that and call it from panfrost_clear(). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* iris: Update comment about 3-component formats and buffer texturesKenneth Graunke2019-10-071-5/+7
| | | | | You can't render to PIPE_BUFFER so there's no reason to prefer RGBX. PBO upload would like to use proper RGB textures as source data.
* iris: Allow packed RGB pbo uploadsChris Wilson2019-10-071-2/+2
| | | | | | | | Hitting any fallback path on Broxton as we require clflushing the whole buffer even for an upload of a subtexture. However, since gallium provides a pbo upload path, allow it to sample packed RGB if supported. Reviewed-by: Kenneth Graunke <[email protected]>
* amd: Move all amd/common code that depends on LLVM to amd/llvm.Timur Kristóf2019-10-085-5/+9
| | | | | | | | | | | | | This commit is a step towards the goal of being able to build RADV without LLVM. In the future we would like to offer the option to use RADV solely with ACO. There is still a need for the common AMD code located in amd/common but the LLVM specific parts need to be separated. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Marek Olšák <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* nvc0: add support for GL_EXT_demote_to_helper_invocationIlia Mirkin2019-10-073-0/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/tgsi: add support for DEMOTE and READ_HELPER opcodesIlia Mirkin2019-10-073-4/+25
| | | | | | | | | | This mirrors the intrinsics in the GLSL IR. One could imagine an alternate definition where reading the semantic would account for the READ_HELPER functionality, but that feels potentially dodgy and could be subject to CSE unpleasantness. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use simple_mtx_t instead of mtx_tMarek Olšák2019-10-079-50/+51
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-0739-73/+84
| | | | | | | | | u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <[email protected]>
* util: use simple_mtx_t for util_rangeMarek Olšák2019-10-071-5/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* winsys/radeon: initialize SIMD properties in radeon_infoMarek Olšák2019-10-071-0/+3
| | | | | | | | | This was missed when I added them. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1839 Fixes: 0692ae34e93 ("ac: move ac_get_num_physical_sgprs into radeon_info") Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* iris: Drop vtbl usage for some load_register callsKenneth Graunke2019-10-071-5/+4
| | | | We can just call the actual functions directly.
* iris/state: Move reg/mem load/store functions earlier in fileJordan Justen2019-10-071-124/+122
| | | | Signed-off-by: Jordan Justen <[email protected]>
* meson: drop duplicate inc_nir from libirisEric Engestrom2019-10-071-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: use idep_nir instead of libnir in pipe-loaderEric Engestrom2019-10-071-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: use idep_nir instead of libnir in haiku softpipeEric Engestrom2019-10-071-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: use idep_nir instead of libnir in gallium nineEric Engestrom2019-10-071-2/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: use idep_nir instead of libnir in libclnirEric Engestrom2019-10-071-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: use idep_nir instead of libnir in libnouveauEric Engestrom2019-10-071-3/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: add missing idep_nir_headers in iris_gen_libsEric Engestrom2019-10-071-2/+2
| | | | | | Fixes: 4929f020c37eac5b07f9 ("iris: better SBE") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* iris: Drop bonus parameters from iris_init_*_context()Kenneth Graunke2019-10-073-27/+10
| | | | Nothing uses vtbl or dbg, and screen is available from the batch.
* Revert "iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaround"Kenneth Graunke2019-10-071-23/+0
| | | | | | | This reverts commit 4f857423b3c095516e553b976b41969c2b9721fa. It caused GPU hangs on all affected platforms, in e.g. Piglit bin/stencil-twoside -auto -fbo.
* Revert "Revert "st/dri2: Implement DRI2bufferDamageExtension""Boris Brezillon2019-10-073-0/+53
| | | | | | | This reverts commit 19546108d3dd5541a189e36df4ea83b3f519e48f. This commit breaks the build because lima implements ->set_damage_region(). I guess we'll need more discussion before removing the ->set_damage_region() hook.
* Revert "st/dri2: Implement DRI2bufferDamageExtension"Boris Brezillon2019-10-073-53/+0
| | | | | | | | | | | | | | This reverts commit 492ffbed63a2a62759224b1c7d45aa7923d8f542. BACK_LEFT attachment can be outdated when the user calls KHR_partial_update(), leading to a damage region update on the wrong pipe_resource object. Let's not expose the ->set_damage_region() method until the core is fixed to handle that properly. Cc: [email protected] Signed-off-by: Boris Brezillon <[email protected]> Acked-by: Daniel Stone <[email protected]>
* gitlab-ci: Move LAVA-related files into top-level ci dirTomeu Vizoso2019-10-069-1741/+0
| | | | | | | In preparation for testing drivers other than Panfrost in LAVA labs. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gitlab-ci: Run dEQP on devices with PanfrostTomeu Vizoso2019-10-063-53/+40
| | | | | | | | | | | Include Panfrost's gitlab.ci.yml file from Mesa's main .gitlab-ci.yml so we test on devices with Panfrost. This uses LAVA to schedule jobs in the devices and will be the base for testing Etnaviv, Lima, etc. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* iris: Hack up a SKL/Gen9LP PS push constant fifo depth workaroundKenneth Graunke2019-10-051-0/+23
| | | | | | | | | | | This is a port of Nanley's 904c2a617d86944fbdc2c955f327aacd0b3df318 from i965 to iris. One concern is that iris uses larger batches, and also emits far fewer commands, so we may come closer to the 500 limit within a batch, and could need to supplement this with actual counting. Manhattan 3.0 had 239 3DSTATE_CONSTANT_PS packets in a batch, Unigine Valley had 155. So it seems like we're still in the realm of safety.
* iris: Refactor push constant allocation so we can reuse itKenneth Graunke2019-10-051-9/+22
| | | | | We'll need this for a workaround shortly. While refactoring, also improve the comment slightly.
* etnaviv: set texture INT_FILTER bitJonathan Marek2019-10-051-1/+2
| | | | | | | This should improve texture sampling performance on GC3000. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: implement texture comparatorJonathan Marek2019-10-056-5/+51
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: update headers from rnndbJonathan Marek2019-10-053-31/+40
| | | | | | | Update to etna_viv commit 7ff8029. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* st/dri: Perform MSAA downsampling for __DRI2_THROTTLE_COPYSUBBUFFERKenneth Graunke2019-10-051-2/+4
| | | | | | | | | | | | | | glXCopySubBufferMESA copies data from the back buffer to the front, so it needs to perform a MSAA downsampling operation just like glXSwapBuffers would. Currently, the CopySubBuffer implementations supply a throttle reason of __DRI2_THROTTLE_SWAPBUFFERS, so they hit this path and work today. But we'd like to avoid swapbuffer throttling in this case, so the next patch will change that reason. Tested-by: Michel Dänzer <[email protected]> # DRI3 only Reviewed-by: Michel Dänzer <[email protected]>
* r600: Fix interpolateAtCentroidGert Wollny2019-10-044-1/+14
| | | | | | | | | | If the instruction interpolateAtCentroid is used the extra interpolator must also be enabled in the state. Fixes: fs-interpolateatcentroid-block Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* panfrost: Get rid of the flush in panfrost_set_framebuffer_state()Boris Brezillon2019-10-031-43/+3
| | | | | | | | | Now that we have track inter-batch dependencies, the flush done in panfrost_set_framebuffer_state() is no longer needed. Let's get rid of it. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Kill the explicit serialization in panfrost_batch_submit()Boris Brezillon2019-10-031-12/+0
| | | | | | | | | Now that we have all the pieces in place to support pipelining batches we can get rid of the drmSyncobjWait() at the end of panfrost_batch_submit(). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Do fine-grained flushing when preparing BO for CPU accessesBoris Brezillon2019-10-032-19/+12
| | | | | | | | | | | | | We don't have to flush all batches when we're only interested in reading/writing a specific BO. Thanks to the panfrost_flush_batches_accessing_bo() and panfrost_bo_wait() helpers we can now flush only the batches touching the BO we want to access from the CPU. This fixes the dEQP-GLES2.functional.fbo.render.texsubimage.* tests. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Make sure the BO is 'ready' when picked from the cacheBoris Brezillon2019-10-033-24/+110
| | | | | | | | This is needed if we want to free the panfrost_batch object at submit time in order to not have to GC the batch on the next job submission. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add flags to reflect the BO imported/exported stateBoris Brezillon2019-10-032-2/+8
| | | | | | | | | Will be useful to make the ioctl(WAIT_BO) call conditional on BOs that are not exported/imported (meaning that all GPU accesses are known by the context). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add a panfrost_flush_batches_accessing_bo() helperBoris Brezillon2019-10-032-0/+35
| | | | | | | | This will allow us to only flush batches touching a specific resource, which is particularly useful when the CPU needs to access a BO. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
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