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* panfrost: Refactor texture targetsAlyssa Rosenzweig2019-06-186-27/+81
| | | | | | | | | | | | | | | | | This combines the two cmdstream bits "is_3d" and "is_not_cubemap" into a single 2-bit texture target selection, noticing it's the same as the 2-bit selection in Midgard and Bifrost texturing ops. Accordingly, we share this definition and add the missing entry for 1D/buffer textures. This requires a nontrivial (but functionally similar) refactor of all parts of the driver to use the new definitions appropriately. Theoretically, this should add support for buffer textures, but that's obviously not tested and probably wouldn't work. While doing so, we notice the sRGB enable bit, which we document and decode as well here so we don't forget about it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Figure out job requirements in pan_job.cRohan Garg2019-06-183-8/+16
| | | | | | | | Requirements for a job should be figured out in pan_job.c v2: [Alyssa] Fix early return Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Reset job counters once the job is submittedRohan Garg2019-06-182-5/+4
| | | | | | Move the reset out of frame invalidation into job submission Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Initial implementation of panfrost_job_submitRohan Garg2019-06-183-5/+23
| | | | | | | | Start fleshing out panfrost_job v2: [Alyssa: Remove unused variable, warning introduced] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl_hw: add YUV supportGurchetan Singh2019-06-181-0/+6
| | | | | | Add corresponding entries from p_format.h Reviewed-by: Emil Velikov <[email protected]>
* virgl: sync to virglrenderer virgl_hw.hGurchetan Singh2019-06-181-3/+10
| | | | | | | It's nice to keep these two files in sync, as they define guest userspace <---> host userspace communcation. Reviewed-by: Emil Velikov <[email protected]>
* panfrost/midgard: Enable autovectorizationAlyssa Rosenzweig2019-06-181-2/+1
| | | | | | Enable nir_opt_vectorize. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add support for TXS instructionsBoris Brezillon2019-06-183-2/+60
| | | | | | | | | | | | | This patch adds support for nir_texop_txs instructions which are needed to support the OpenGL textureSize() function. This is also needed to support RECT texture sampling which is currently lowered to 2D sampling + a TXS() instruction by the nir_lower_tex() helper. Changes in v2: * Split options for the 1st and 2nd tex lowering passes Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Prepare things to support non-native texture opsBoris Brezillon2019-06-181-16/+19
| | | | | | | | | We are about to add support for the TXS (texture size) op which is not implemented using a midgard texture instruction. Let's rename emit_tex() into emit_texop_native() and repurpose emit_tex() as a dispatcher. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move sysval upload logic out of panfrost_emit_for_draw()Boris Brezillon2019-06-182-17/+54
| | | | | | | | | | | | We're about to add more sysval types, and panfrost_emit_for_draw() is big enough, so let's move the sysval upload logic in a separate function. We also add one sub-function per sysval type to keep the panfrost_upload_sysvals() small/readable. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Make the sysval logic more genericBoris Brezillon2019-06-181-22/+39
| | | | | | | | | | | We are about to add support for nir_texop_txs which requires adding a sysval/uniform containing the texture size. Let's change the emit_sysval_read() prototype to take a nir_instr object instead of a nir_intrinsic_instr one so we can re-use this function when emitting a sysval for a txs instruction. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adapt to constant name change in UABITomeu Vizoso2019-06-181-1/+1
| | | | | | | We hadn't updated the kernel header after the driver got into mainline. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: ci: Update resultsTomeu Vizoso2019-06-181-15/+0
| | | | | | | Alyssa fixed some failing tests last night. Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* v3d: only flush jobs accessing the query BO when reading query resultsIago Toral Quiroga2019-06-181-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: add a helper function to flush jobs using a BOIago Toral Quiroga2019-06-182-0/+12
| | | | | | v2: use _mesa_set_search() (Eric) Reviewed-by: Eric Anholt <[email protected]>
* iris: Support more RGBX pipe formats.Kenneth Graunke2019-06-171-2/+13
| | | | | | | | Without them, the state tracker falls back to an RGBA format, but it doesn't always manage to override the swizzle for us. So we lose the information that the API expects an X channel, where alpha is garbage and reads back as 1. We have no equivalent ISL RGBX format for these, so we just use RGBA directly and override the swizzle in all cases.
* iris: Make resource_copy_region handle packed depth-stencil resources.Kenneth Graunke2019-06-171-0/+10
| | | | | | Also copy along the separate stencil buffer if needed. Fixes Piglit's arb_copy_image-formats.
* iris: Order CS stall and TC invalidate for format reinterpretation hacksKenneth Graunke2019-06-171-3/+2
| | | | | | | | This should ensure the TC invalidate happens after the stall. Fixes KHR-GL43.copy_image.functional which does a CopyImage (blorp_copy) from a buffer (using R8G8B8A8_UINT), then GetTexImage to read back the original image (using R10G10B10A2_UNORM).
* iris: Be more aggressive at post-format-reintepret TC invalidate hackKenneth Graunke2019-06-171-8/+5
| | | | | | | | | | | | | | When copying/blitting with format reinterpretation, we invalidate the texture cache before/after. Before is so the source of the copy works, and after is to get rid of our new data in the "wrong" format to protect future attempts to sample. When I ported these hacks to iris, I tried to be cautious by only bothering with the hacks if the batch referenced the BO. This makes some sense for the before case. If it isn't referenced, the texture cache can't really have any data for the BO (since it's also invalidated between batches). But we still need to do the after case regardless, as we've just polluted the cache with hazardous entries.
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-171-1/+2
| | | | | | | | | | | | | | | | When the host virglrenderer is an older version that doesn't check the sRGB write control feature, or when the guest kernel doesn't support CAPS v2, then the guest will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting 3.3 with earlier guest mesa versions. By also checking the host feature check version this regression can be avoided. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921 Fixes: 2845939d6a72 virgl: Set sRGB write control CAP based on host capabilities Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* freedreno/a6xx: disallow UBWC for x24s8Rob Clark2019-06-171-4/+15
| | | | | | | | | Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: un-swap X24S8_UINTRob Clark2019-06-172-5/+6
| | | | | | | | | | | | | | | | | | | The stencil is actually in the .w component, but we used to use SWAP to remap the channels. This doesn't work when tiled/ubwc. Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d_array dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_cube dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d_array dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube dEQP-GLES31.functional.stencil_texturing.misc.base_level dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil Signed-off-by: Rob Clark <[email protected]>
* gallium: Remove unused util_ringbufferCaio Marcelo de Oliveira Filho2019-06-174-193/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Don't use u_ringbuffer for lp_scene_queueCaio Marcelo de Oliveira Filho2019-06-171-36/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inline the ring buffer and signal logic into lp_scene_queue instead of using a u_ringbuffer. The code ends up simpler since there's no need to handle serializing data from / to packets. This fixes a crash when compiling Mesa with LTO, that happened because of util_ringbuffer_dequeue() was writing data after the "header packet", as shown below struct scene_packet { struct util_packet header; struct lp_scene *scene; }; /* Snippet of old lp_scene_deque(). */ packet.scene = NULL; ret = util_ringbuffer_dequeue(queue->ring, &packet.header, sizeof packet / 4, return packet.scene; but due to the way aliasing analysis work the compiler didn't considered the "&packet->header" to alias with "packet->scene". With the aggressive inlining done by LTO, this would end up always returning NULL instead of the content read by util_ringbuffer_dequeue(). Issue found by Marco Simental and iThiago Macieira. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884 Reviewed-by: Roland Scheidegger <[email protected]>
* panfrost/midgard: Simplify 2D array logicAlyssa Rosenzweig2019-06-171-4/+1
| | | | | | It shouldn't matter if we stick a z in for non-arrays, anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Handle non-zero component in storeAlyssa Rosenzweig2019-06-172-8/+9
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Apply writemask to LUTsAlyssa Rosenzweig2019-06-172-3/+8
| | | | | | Fixes LUT instructions with NIR registers. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* amd: update addrlibMarek Olšák2019-06-171-0/+24
| | | | | Acked-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICESNicolai Hähnle2019-06-171-1/+4
| | | | | | This fixes piglit [email protected]@gs-max-output on gfx9. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* panfrost: Cleanup default blend modeAlyssa Rosenzweig2019-06-171-19/+8
| | | | | | | Just encode the Mali magic number for `replace` rather than awkwardly forcing Gallium structures through. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Don't accidentally include blend shaderAlyssa Rosenzweig2019-06-171-0/+2
| | | | | | Some residual dirty state can leak through across frames; zero this out. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Use typeless moves internallyAlyssa Rosenzweig2019-06-173-39/+15
| | | | | | | | We switch all fmov to (i)mov, following the NIR switch. This simplifies some code surrounding blend shaders and should have no functional changes elsewhere. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCEChia-I Wu2019-06-174-25/+92
| | | | | | | | | | | | | | | | | | | | | | | When the resource to be mapped is busy and the backing storage can be discarded, reallocate the backing storage to avoid waiting. In this new path, we allocate a new buffer, emit a state change, write, and add the transfer to the queue . In the PIPE_TRANSFER_DISCARD_RANGE path, we suballocate a staging buffer, write, and emit a copy_transfer (which may allocate, memcpy, and blit internally). The win might not always be clear. But another win comes from that the new path clears res->valid_buffer_range and does not clear res->clean_mask. This makes it much more preferable in scenarios such as access = enough_space ? GL_MAP_UNSYNCHRONIZED_BIT : GL_MAP_INVALIDATE_BUFFER_BIT; glMapBufferRange(..., GL_MAP_WRITE_BIT | access); memcpy(...); // append new data glUnmapBuffer(...); Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-174-0/+148
| | | | | | | | | We are going support reallocating the HW resource for a virgl_resource. When that happens, the virgl_resource needs to be rebound to the context. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: save virgl_hw_res in virgl_transferChia-I Wu2019-06-175-14/+22
| | | | | | | | | | When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is properly supported, virgl_transfer might refer to a different virgl_hw_res than virgl_resource does. We need to save the virgl_hw_res and use the saved one. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* virgl: add resource_reference to virgl_winsysChia-I Wu2019-06-174-32/+21
| | | | | | | | It works similar to pipe_resource_reference but is for virgl_hw_res. It can also replace resource_unref. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Alexandros Frantzis <[email protected]>
* panfrost/midgard: Add rounding mode specific opcodesAlyssa Rosenzweig2019-06-173-20/+49
| | | | | | | This adds a set of opcodes for performing moves and type conversions with respect to particular rounding modes, required for OpenCL. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Drop draws with complete scissorAlyssa Rosenzweig2019-06-172-4/+20
| | | | | | | | The hardware support for scissoring requires minimally 1 pixel to be drawn. If the scissor culls *everything*, we need to drop the draw entirely early on. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable pipelining temporarilyAlyssa Rosenzweig2019-06-171-2/+4
| | | | | | | | Pipelined rendering is important for performance but is not working right these days. Disable it for correctness until the panfrost_job refactor is enabled and we can do it right. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/mfbd: Handle rendering to linear mipmapAlyssa Rosenzweig2019-06-171-4/+18
| | | | | | | In anticipation of more general mipmapping support, we implemented support for rendering to linear mipmaps (a very simple case). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement sampling from non-zero initial levelsAlyssa Rosenzweig2019-06-171-15/+14
| | | | | | | | In preparation for more complex mipmap operations. glGenerateMipmap() in particular, as implemented by u_blitter, requires reading from non-zero initial mip levels. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Resource management for linear 2D texture arraysAlyssa Rosenzweig2019-06-171-1/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Adjust swizzles for 2D arraysAlyssa Rosenzweig2019-06-171-0/+10
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Set array_size to permit array texturesAlyssa Rosenzweig2019-06-171-0/+11
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Decode array texturesAlyssa Rosenzweig2019-06-172-4/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Implement 3D texture resource managementAlyssa Rosenzweig2019-06-171-5/+45
| | | | | | Passes dEQP-GLES3.functional.texture.format.unsized.*3d* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Specify 3D in texture descriptorAlyssa Rosenzweig2019-06-172-1/+4
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fix 3D texture masks/swizzlesAlyssa Rosenzweig2019-06-171-3/+8
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add swizzle_of/mask_of helpersAlyssa Rosenzweig2019-06-171-6/+30
| | | | | | These make manipulating vectors in the Midgard compiler easier. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable helper invocations when texturingAlyssa Rosenzweig2019-06-174-76/+25
| | | | | | | | | | | | | | | | | | | it turns out we have explicit control over helper invocations; if a particular bit in the fragment shader descriptor is set, helper invocations are launched; if it clear, they are not. Helper invocations are required whenever computing derivatives, whether explicitly (dFdx/dFdy) *or* implicitly (any texturing). Accordingly, we set this bit when texturing to fix edge case behaviour (literally, haha). Thank you to Jason Ekstrand and Ilia Mirkin for pointing out the representative dEQP test failed along triangle edges and for suggesting helper invocations / derivatives as a list of suspect pieces (which led to discovering the helper invocations enable bit in the first place). Ideally we would use the new NIR analysis pass for this, but that hasn't landed quite yet. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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