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* radeonsi/nir: Use nir stripping passConnor Abbott2019-03-121-0/+5
| | | | | | | | | This reduces compilation time for my shader-db collection from around 40 seconds to 30, vs. 19 seconds for TGSI. There are still some shaders that TGSI caches but NIR doesn't, partly because of more aggressive cross-stage optimizations with NIR. Reviewed-by: Timothy Arceri <[email protected]>
* iris: Flag fewer dirty bits in BLORPSagar Ghuge2019-03-111-3/+27
| | | | | | | | | v2: 1) Skip flagging IRIS_DIRTY_DEPTH_BUFFER if BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set (Kenneth Graunke) 2) Add missing flags (Kenneth Graunke) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* panfrost: Identify fragment_extra flagsAlyssa Rosenzweig2019-03-123-10/+30
| | | | | | | | | | | | | | | | The fragment_extra structure contains additional fields extending the MRT framebuffer descriptor, snuck in between the main framebuffer descriptor and the render targets. Its fields include those related to transaction elimination and depth/stencil buffers. This patch identifies the flags field (previously just "unk" with some magic values) as well as identifying some (but not all) flags set by the driver. The process of identifying flags brought a bug to light where transaction elimination (checksumming) could not be enabled unless AFBC was in-use. This issue is now resolved. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Document "depth-buffer writeback" bitAlyssa Rosenzweig2019-03-122-1/+9
| | | | | | | | | This bit, if set, causes the depth buffer to be copied from GPU tile memory to the provided depth buffer in main memory. If not set, the GPU will not access the main memory (saving considerable memory bandwidth if depth results are not actually used). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Support linear depth texturesAlyssa Rosenzweig2019-03-121-2/+4
| | | | | | | | | | | This combination has not yet been seen "in the wild" in traces, but to support linear depth FBOs, ~bruteforce reveals this bit pattern is necessary. It's not yet clear why the meanings of 0x1 and 0x2 are essentially flipped (tiled vs linear for colour, linear vs some sort of tiled for depth). Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Allocate dedicated slab for linear BOsAlyssa Rosenzweig2019-03-122-15/+22
| | | | | | | | | | | | | | Previously, linear BOs shared memory with each other to minimize kernel round-trips / latency, as well as to work around a bug in the free_slab function. These concerns are invalid now, but continuing to use the slab allocator for BOs resulted in memory allocation errors. This issue was aggravated, though not introduced (so not a real regression) in the previous commit. v2 (unreviewed): Fix bug in v1 preventing munmaps from working Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Determine framebuffer format bits lateAlyssa Rosenzweig2019-03-121-17/+42
| | | | | | | | | | | Again, these formats are only properly known at the time of fragment job emit. Rather than hardcoding the format, at least for MFBD we begin to construct the format bits on-demand. This cleans up the code, futureproofs for ES3 framebuffer formats, and should fix bugs regarding FBO colour swizzles. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Delay color buffer setupAlyssa Rosenzweig2019-03-121-43/+50
| | | | | | | | | In an effort to cleanup framebuffer management code, we delay colour buffer setup until the FRAGMENT job is actually emitted, allowing the AFBC and linear codepaths to be unified. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Combine has_afbc/tiled in layout enumAlyssa Rosenzweig2019-03-123-24/+64
| | | | | | | | AFBC, tiled, and linear BO layouts are mutually exclusive; they should be coupled via a single enum rather than ad hoc checks of booleans. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* panfrost: Cleanup needless if in create_boAlyssa Rosenzweig2019-03-121-30/+26
| | | | | | | | | I'm not sure why we were checking for these additional criteria (likely inherited from some other driver); remove the needless checks to cleanup the code and perhaps fix some bugs down the line. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* gallium/winsys/kms: fix incomplete type compilation failureBrian Paul2019-03-111-0/+1
| | | | | | | | | | Fixes: ../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c: In function ‘kms_sw_displaytarget_from_handle’: ../src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c:402:60: error: dereferencing pointer to incomplete type ‘const struct pipe_resource’ templ->format, ^ Reviewed-by: Mathias Fröhlich <[email protected]>
* drisw: fix incomplete type compilation failureBrian Paul2019-03-111-0/+1
| | | | | | | | | | Fixes: ../src/gallium/winsys/sw/dri/dri_sw_winsys.c: In function ‘dri_sw_displaytarget_display’: ../src/gallium/winsys/sw/dri/dri_sw_winsys.c:255:39: error: dereferencing pointer to incomplete type ‘struct pipe_box’ offset = dri_sw_dt->stride * box->y; ^ Reviewed-by: Mathias Fröhlich <[email protected]>
* panfrost: Add support for PAN_MESA_DEBUGTomeu Vizoso2019-03-126-27/+88
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add support for MIDGARD_MESA_DEBUGTomeu Vizoso2019-03-122-22/+50
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* iris: Fix write enable in pinning of depth/stencil resourcesKenneth Graunke2019-03-111-12/+14
| | | | | | | | | | | | | | We may bind new Z/S buffers (which come via the framebuffer CSO, triggering IRIS_DIRTY_DEPTH_BUFFER), but with writes disabled. The next draw may enable Z or S writes (which come via the ZSA CSO, triggering IRIS_DIRTY_WM_DEPTH_STENCIL), which requires us to update our pin to have the write flag. So, update pinning if either dirty flag changes. To clarify, pass cso_zsa to the pinning function rather than pulling the random values out of ice->state, which unfortunately have to exist for the resolve code since iris_depth_stencil_alpha_state only exists in iris_state.c.
* iris: Refactor depth/stencil buffer pinning into a helper.Kenneth Graunke2019-03-111-37/+28
| | | | | | | This avoids the code duplication that caused me to put things in the wrong place in the previous commit. One used to have extra flushes, but we moved those out so now these are identical and can be easily shared.
* iris: Move depth/stencil flushes so they actually do somethingKenneth Graunke2019-03-112-4/+5
| | | | | | | | | | | | | | Commit d6dd57d43cd (iris: Add missing depth cache flushes) added the depth/stencil flushes to the wrong place. I meant to add them to the iris_upload_dirty_render_state code that emits the packets, but I accidentally added them to the nearly identical looking code in iris_restore_render_saved_bos. This meant we missed the actual flushing at draw time, but instead did pointless flushing on the first draw in a batch where things are already flushed anyway. This commit moves them to iris_resolve.c, next to the depth prepares, similar to what we do for color buffers. i965 does them elsewhere, but I'm not sure why - this seems like the most consistent place.
* st/dri: allow direct UYVY importChristian Gmeiner2019-03-111-0/+2
| | | | | | | Push this format to the pipe driver unchanged. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Fix TES gl_PatchVerticesIn handling.Kenneth Graunke2019-03-112-3/+11
| | | | | | | | | | | | | | | | 1. If we switch the TCS for one with a different number of output vertices, then the TES's gl_PatchVerticesIn value will change. We need to re-upload in this case. For now, re-emit constants whenever the TCS/TES are swapped out. 2. If there is no TCS, then we can't grab gl_PatchVerticesIn from the TCS info. Since it's a passthrough, we can just use the primitive's patch count (like the TCS gl_PatchVerticesIn does). Fixes KHR-GL45.tessellation_shader.single.max_patch_vertices and KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Rework default tessellation level uploadsKenneth Graunke2019-03-112-39/+33
| | | | | | | | | | | Now that we've added a system value uploading mechanism, we may as well reuse the same system for default tessellation levels. This simplifies the state upload code a bit. Also fixes: KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_tessLevel Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* iris: Face should be a system value.Timur Kristóf2019-03-111-0/+1
| | | | | | | | | | | | This patch adds PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL which despite its name is not a TGSI-specific capability, just lets the state tracker know that it should generate a system value for FACE. This is needed if we want to run tgsi_to_nir on iris. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* vc4: Switch the post-RA scheduler over to the DAG datastructure.Eric Anholt2019-03-111-110/+73
| | | | Just a small code reduction from shared infrastructure.
* v3d: Use the DAG datastructure for QPU instruction scheduling.Eric Anholt2019-03-111-3/+3
| | | | Just a small code reduction from shared infrastructure.
* vc4: Reuse list_for_each_entry_rev().Eric Anholt2019-03-111-2/+2
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* vc4: Switch over to using the DAG datastructure for QIR scheduling.Eric Anholt2019-03-111-79/+55
| | | | Just a small code reduction from shared infrastructure.
* freedreno/a6xx: Remove extra parensKristian H. Kristensen2019-03-111-1/+1
| | | | | | There's a warning about this now. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: Use c_vis_args and no_override_init_argsKristian H. Kristensen2019-03-111-1/+1
| | | | Signed-off-by: Kristian H. Kristensen <[email protected]>
* iris: Fix backface stencil write conditionKenneth Graunke2019-03-101-1/+1
| | | | A bit too much search and replace here.
* panfrost/drm: Cast pointer to u64 to fix warningAlyssa Rosenzweig2019-03-101-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add backend targeting the DRM driverTomeu Vizoso2019-03-108-74/+466
| | | | | | | | | | | | | | | | | | | This backend interacts with the new DRM driver for Midgard GPUs which is currently in development. When using this backend, Panfrost has roughly on-par functionality as when using the non-DRM driver from Arm. Alyssa Rosenzweig: To do so, we implement additional routines for runtime GPU version detection and fencing. We cleanup some duplicate code interfering with the new driver. We fix a long-standing memory leak which is aggravated on the new driver. Finally, we implement BO import/export in a way compatible with the new driver. These changes are squashed to preserve bisectability given the hard-to-track ABI shifts in the nondrm module Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Add gem_handle to panfrost_memory and panfrost_boTomeu Vizoso2019-03-102-0/+3
| | | | | | | It will be used by the DRM backend to store GEM handles from the kernel. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* freedreno/a6xx: more bcolor fixesRob Clark2019-03-101-2/+2
| | | | | | | | | | | | | | Non-zero offset wasn't working, which breaks a bunch of dEQP-GLES31.functional.texture.border_clamp.formats.* when doing sharded deqp runs (because order of tests changes, resulting in different texture state bound.. deqp doesn't really clean up it's gl state between tests very well) Previously, if additional textures were bound, due to using too small of a bcolor_entry size, the last 32bytes of the bcolor_entry would be overwritten. Signed-off-by: Rob Clark <[email protected]>
* panfrost: move #include to fix compilationEric Engestrom2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | In standalone.h, the struct gl_context type is not declared by #includ'ing mtypes.h: In file included from src/gallium/drivers/panfrost/midgard/cmdline.c:24: src/compiler/glsl/standalone.h:46:14: warning: ‘struct gl_context’ declared inside parameter list will not be visible outside of this definition or declaration struct gl_context *ctx); ^~~~~~~~~~ This causes the following compilation failure: src/gallium/drivers/panfrost/midgard/cmdline.c: In function ‘compile_shader’: src/gallium/drivers/panfrost/midgard/cmdline.c:58:61: error: passing argument 4 of ‘standalone_compile_shader’ from incompatible pointer type [-Werror=incompatible-pointer-types] prog = standalone_compile_shader(&options, 2, argv, &local_ctx); ^~~~~~~~~~ In file included from src/gallium/drivers/panfrost/midgard/cmdline.c:24: src/compiler/glsl/standalone.h:43:28: note: expected ‘struct gl_context *’ but argument is of type ‘struct gl_context *’ struct gl_shader_program * standalone_compile_shader( ^~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: e67e0726372ab65f4104 "panfrost: Implement Midgard shader toolchain" Cc: Alyssa Rosenzweig <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* panfrost: fix tgsi_to_nir() callEric Engestrom2019-03-091-1/+1
| | | | | | | Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109945 Fixes: 7da251fc721360fc28b9 "panfrost: Check in sources for command stream" Cc: Alyssa Rosenzweig <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* Revert "d3dadapter9: Support software renderer on any DRI device"Axel Davy2019-03-091-20/+8
| | | | | | | | This reverts commit 0d0847659385e298badd6ef6ca4d0a9e537ae288. It makes gitlab's travis fail. Revert until patch is fixed. Signed-off-by: Axel Davy <[email protected]>
* st/nine: Change a few advertised capsAxel Davy2019-03-091-3/+3
| | | | | | | | | | | | | | | | | | | Most hw on the native platform advertise these caps this way. D3DCAPS_READ_SCANLINE: We don't really have hardware support for that, but many games don't even check the flag, and expect GetRasterStatus to work, which is why we emulated it with a timer (like wine). So we may as well advertise the cap. D3DCURSORCAPS_LOWRES: I don't know what is the status of this on X11, but I don't know of any dx9 game running at height < 400 either. D3DPTEXTURECAPS_TEXREPEATNOTSCALEDBYSIZE: The cap should correspond to what the current generation of hw is doing. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
* st/nine: Do not advertise CANMANAGERESOURCEAxel Davy2019-03-091-1/+1
| | | | | | | It doesn't seem the main vendors advertise it. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Patrick Rudolph <[email protected]>
* st/nine: Do not advertise support for D15S1 and D24X4S4Axel Davy2019-03-091-2/+2
| | | | | | | | | | | The former is supported on Matrox cards but no other hw. The latter isn't supported anywhere. It is fine to not advertise them as supported, and it could prevent apps to trigger weird rendering paths. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* d3dadapter9: Support software renderer on any DRI devicePatrick Rudolph2019-03-091-8/+20
| | | | | | | | | | | | If D3D_ALWAYS_SOFTWARE is set for debugging purposes, run on any DRI enabled platform. Instead of probing for a compatible gallium driver (which might fail if there's none) always use the KMS DRI software renderer. Allows to run nine on i915 when D3D_ALWAYS_SOFTWARE=1. Signed-off-by: Patrick Rudolph <[email protected]> Reviewed-by: Axel Davy <[email protected]>
* st/nine: Disable depth write when nothing gets updatedAxel Davy2019-03-091-1/+4
| | | | | | | | | | | I do not see any perf impact on radeonsi, but it seems iris needs this. It seems something sensible to do. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Timur Kristóf <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Andre Heider <[email protected]>
* virgl: Return an error if we use fp64 on top of GLESElie Tournier2019-03-091-0/+13
| | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: <Gurchetan Singh [email protected]>
* virgl: Set PIPE_CAP_DOUBLES when running on GLES This is a lie but no known ↵Elie Tournier2019-03-091-1/+2
| | | | | | | app use fp64. Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: <Gurchetan Singh [email protected]>
* virgl: Add a caps to advertise GLES backendElie Tournier2019-03-091-0/+1
| | | | | Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: <Gurchetan Singh [email protected]>
* freedreno/ir3: fix ir3_cmdline harderRob Clark2019-03-081-2/+2
| | | | | | Fixes: 45271702ec9 freedreno: fix ir3_cmdline build Fixes: 7530d4abfcf glsl/freedreno/panfrost: pass gl_context to the standalone compiler Signed-off-by: Rob Clark <[email protected]>
* st/dri: Set the PIPE_BIND_SHARED flag on create_image_with_modifiers.Eric Anholt2019-03-081-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | With createImage(), the caller was expected to set a SHARED flag if they needed the ability to get a GEM handle. DRI3, wayland, and gbm all set it, EGL_MESA_drm_image passes it through, and surfaceless doesn't need it because there's no way to request a handle. With the new createImageWithModifiers() DRI method to replace it, the expectation is that you'll always be able to share the buffer, so the flag is unnecessary in its arguments. However, we do need to tell gallium about this expectation. Without this, kmscube's modifiers path using gbm_bo_create_with_modifiers(&modifier, 1) instead of gbm_bo_create(SCANOUT | SHARED) will call the driver's resource_create() function wtih PIPE_BIND_SHARED unset, so the driver (particularly renderonly drivers) may allocate in such a way that it can't return an answer from gbm_bo_get_handle(). I used to have a hack in v3d using count==1 && modifier==LINEAR to indicate that you wanted SHARED anyway, but that was dropped recently. Fixes: 59527a36e975 ("v3d: Restructure RO allocations using resource_from_handle.") Reviewed-by: Kristian H. Kristensen <[email protected]>
* iris: Use copy_region and staging resources to avoid transfer stallsKenneth Graunke2019-03-084-14/+161
| | | | | | | | | | | | This is similar to intel_miptree_map_blit and intel_buffer_object.c's temporary blits in i965. Improves performance of DiRT Rally by 20-25% by eliminating stalls. Breaks piglit's spec/arb_shader_image_load_store/host-mem-barrier, by using the GPU to do uploads, exposing a st/mesa issue where it doesn't give us memory_barrier() calls. This is a pre-existing issue and will be fixed by a later patch (currently out for review).
* iris: Track last VS URB entry sizeSagar Ghuge2019-03-083-0/+11
| | | | | | | | | | | | Return immediately if last VS URB entry size is good enough for BLORP operation v2: Fix comments (Caio) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Kenneth Graunke<[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Refactor code to share 3DSTATE_URB_* packetSagar Ghuge2019-03-083-59/+60
| | | | | | | | | | v2: 1) Set IRIS_DIRTY_URB bit (Caio) 2) Get rid of unnecessary function (Caio) Signed-off-by: Sagar Ghuge <[email protected]> Suggested-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r600: cast pointer to expected typeEric Engestrom2019-03-081-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-By: Gert Wollny <[email protected]>
* pipebuffer: s/PB_ALL_USAGE_FLAGS/PB_USAGE_ALL/Brian Paul2019-03-081-1/+1
| | | | | | | To fix build failure. I guess my meson configuration has assertions disabled for some reason. Trivial fix.
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